# US 9,437,325 B2 · TFT array substrate, display panel and display device

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- Number: US 9,437,325 B2
- Document ID: US9437325B2
- Status: Granted
- Kind: B2
- Application number: 14/466,926
- Filed: 2014-08-22
- Published: 2015-11-26
- Granted: 2016-09-06
- Earliest claimed: 2014-05-21
- Assignees: Shanghai Tianma Am-Oled Co., Ltd.; Tianma Micro-Electronics Co., Ltd.
- Applicants: Shanghai Tianma AM-OLED Co., Ltd.; Tianma Micro-Electronics Co., Ltd.
- Inventors: Dong Qian
- Web page: https://patentgrep.com/patent/US9437325B2

## CPC

- G11C 27/04: Shift registers
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/184: {with field-effect transistors, e.g. MOS-FET}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0465: Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
- G09G 2310/0224: Details of interlacing
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/061: for resetting or blanking
- G09G 2330/021: Power management, e.g. power saving
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A TFT array substrate is disclosed. The TFT array substrate includes a plurality of gate lines, and a gate driving circuit connected to the gate lines. The gate driving circuit includes a plurality of stages of shift registers, where odd-numbered stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at opposite ends of the gate lines.

## Claims

### Claim 1

A TFT array substrate, comprising:
a plurality of gate lines; and
a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers, wherein odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
wherein the gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal; the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal,
wherein the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal, wherein i is a positive integer, and
wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal; the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal; and the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.

### Claim 2 (depends on 1)

The TFT array substrate of claim 1, wherein,
the first clock signal terminal of the (i+2)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal; the second clock signal terminal of the (i+2)-th stage of shift register is connected to the first pulse signal line to receive the first pulse signal, and the reset terminal of the (i+2)-th stage of shift register is connected to the fourth pulse signal line to receive the fourth pulse signal; and
the first clock signal terminal of the (i+3)-th stage of shift register is connected to the fourth pulse signal line to receive the fourth pulse signal; the second clock signal terminal of the (i+3)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal; and the reset terminal of the (i+3)-th stage of shift register is connected to the first pulse signal line to receive the first pulse signal.

### Claim 3 (depends on 2)

The TFT array substrate of claim 2, wherein,
the gate driving circuit further comprises an initial signal line; and each stage of the plurality of stages of shift registers further comprises an input terminal and an output terminal, with the output terminal of each stage of the plurality of stages of the shift registers being connected to the respective gate line;
the input terminal of the first stage of shift register is connected to the initial signal line to receive an initial signal; and the input terminal of the k-th stage of shift register is connected to the output terminal of the (k−2)-th stage of shift register to receive an output signal from the output terminal of the (k−2)-th stage of shift register; and
the input terminal of the second stage of shift register is connected to the initial signal line to receive the initial signal; and the input terminal of the j-th stage of shift register is connected to the output terminal of the (j−2)-th stage of shift register to receive an output signal from the output terminal of the (j−2)-th stage of shift register, wherein, k>1, j>2, and k is an odd number, j is an even number.

### Claim 4 (depends on 3)

The TFT array substrate of claim 3, wherein, the shift register comprises: a first capacitor, a second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;
a source electrode of the first transistor is connected to a first level signal line, and a drain electrode of the first transistor is connected to the output terminal through the second capacitor;
a source electrode of the second transistor is connected to a gate electrode of the first transistor, a drain electrode of the second transistor is connected to a second level signal line, and a gate electrode of the second transistor is connected to the reset terminal;
a source electrode of the third transistor is connected to the first level signal line, a drain electrode of the third transistor is connected to the source electrode of the second transistor, and the gate electrode of the third transistor is connected to the output terminal through the second capacitor;
a source electrode of the fourth transistor is connected to the output terminal through the second capacitor and is further connected to the gate electrode of the third transistor, a drain electrode of the fourth transistor is connected to the input terminal, and a gate electrode of the fourth transistor is connected to the first clock signal terminal;
a source electrode of the fifth transistor is connected to the first level signal line, a drain electrode of the fifth transistor is connected to the output terminal, and a gate electrode of the fifth transistor is connected to the first level signal line through the first capacitor and is further connected to the source electrode of the second transistor; and
a source electrode of the sixth transistor is connected to the output terminal, a drain electrode of the sixth transistor is connected to the second clock signal terminal, and a gate electrode of the sixth transistor is connected to the source electrode of the fourth transistor.

### Claim 5 (depends on 4)

The TFT array substrate of claim 4, wherein, all of the transistors are low temperature polycrystalline silicon thin film transistors or PMOS transistors.

### Claim 6 (depends on 2)

The TFT array substrate of claim 2, wherein,
a phase difference between adjacent two of the first pulse signal S1, the second pulse signal S2, the third pulse signal S3 and the fourth pulse signal S4 is a quarter of a pulse cycle.

### Claim 7

A display panel, comprising a TFT array substrate, where the TFT array substrate comprises:
a plurality of gate lines; and
a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers, wherein,
odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
wherein gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal; the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal; and the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal; wherein, i is a positive integer,
wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal; the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal, and
wherein the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.

### Claim 8

A display device, comprising a TFT array substrate, where the TFT array substrate comprises:
a plurality of gate lines; and
a gate driving circuit connected to the gate lines, comprising a plurality of stages of shift registers,
wherein odd-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, even-numbered stages of shift registers from the plurality of stages of shift registers are cascaded-connected to each other, and the odd-numbered stages of shift registers and the even-numbered stages of shift registers are disposed at both ends of the gate lines, respectively,
wherein the gate driving circuit further comprises a first pulse signal line, a second pulse signal line, a third pulse signal line and a fourth pulse signal line, and each of the plurality of stages of shift registers comprises a first clock signal terminal, a second clock signal terminal, and a reset terminal,
wherein the first clock signal terminal of the i-th stage of shift register is connected to the first pulse signal line to receive a first pulse signal; the second clock signal terminal of the i-th stage of shift register is connected to the second pulse signal line to receive a second pulse signal; and the reset terminal of the i-th stage of shift register is connected to the third pulse signal line to receive a third pulse signal; wherein, i is a positive integer,
wherein the first clock signal terminal of the (i+1)-th stage of shift register is connected to the third pulse signal line to receive the third pulse signal; the second clock signal terminal of the (i+1)-th stage of shift register is connected to the fourth pulse signal line to receive a fourth pulse signal, and
wherein the reset terminal of the (i+1)-th stage of shift register is connected to the second pulse signal line to receive the second pulse signal.