# US 9,437,323 B2 · Shift register circuit for preventing malfunction due to clock skew and memory device including the same

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- Number: US 9,437,323 B2
- Document ID: US9437323B2
- Status: Granted
- Kind: B2
- Application number: 14/678,581
- Filed: 2015-04-03
- Published: 2016-05-12
- Granted: 2016-09-06
- Earliest claimed: 2014-11-07
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Soo-Bin Lim
- Web page: https://patentgrep.com/patent/US9437323B2

## CPC

- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C 7/1066: {Output synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/32: Timing circuits
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A shift register circuit may include a first latch capable of latching an input signal in synchronization with a first clock, a first flip-flop capable of latching the output signal of the first latch in synchronization with a second dock having the same skew as the first clock, a second latch capable of latching the output signal of the first flip-flop in synchronization with a third clock having a different skew from the second clock, and a second flip-flop capable of latching the output signal of the second latch circuit in synchronization with a fourth clock having the same skew as the third clock.

## Claims

### Claim 1

A shift register circuit, comprising:
a first D latch capable of latching an input signal in synchronization with a first clock;
a first D flip-flop capable of latching an output signal of the first D latch in synchronization with a second clock having the same skew as the first clock;
a second D latch capable of latching an output signal of the first D flip-flop in synchronization with a third clock having a different skew from the second clock; and
a second D flip-flop capable of latching an output signal of the second D latch circuit in synchronization with a fourth clock having the same skew as the third clock.

### Claim 2 (depends on 1)

The shift register circuit of claim 1, wherein:
each of the first D latch and the second D latch latches a corresponding input signal when a corresponding input clock has a logic low level; and
each of the first D flip-flop and the second D flip-flop latches a corresponding input signal at a falling edge of a corresponding input clock.

### Claim 3 (depends on 1)

The shift register circuit of claim 1, wherein:
each of the first D latch and the second D latch latches a corresponding input signal when the corresponding input clock has a logic high level; and
each of the first D flip-flop and the second D flip-flop latches a corresponding input signal at a rising edge of a corresponding input clock.

### Claim 4

A shift register circuit, comprising:
a first region and a second region,
wherein the first region comprises:
a first D latch capable of latching an input signal in synchronization with a first clock, and
1st to Nth first D flip-flops connected in series and capable of sequentially latching an output signal of the first D latch in synchronization with the first clock, wherein N is an integer of 2 or more;
wherein the second region comprises:
a second D latch capable of latching an output signal of the Nth first flip-flop in synchronization with a second clock; and
1st to Mth second D flip-flops connected in series and capable of sequentially latching an output signal of the second D latch in synchronization with the second clock, wherein M is an integer of 2 or more; and
wherein a distance between the Nth first D flip-flop of the first region and the second D latch of the second region is at least 10 times longer than a distance between D latches and D flip-flops in previous and next stages within one of the first and second regions.

### Claim 5 (depends on 4)

The shift register circuit of claim 4, wherein:
each of the first D latch and the second D latch latches a corresponding input signal when a corresponding input clock has a logic low level; and
each of the 1st to Nth D first flip-flops and the 1st to Mth second D flip-flops latches a corresponding input signal at a falling edge of a corresponding input clock.

### Claim 6 (depends on 4)

The shift register circuit of claim 4, wherein:
each of the first D latch and the second D latch latches a corresponding input signal when a corresponding input clock has a logic high level; and
each of the 1st to Nth first D flip-flops and the 1st to Mth second D flip-flops latches a corresponding input signal at a rising edge of a corresponding input clock.

### Claim 7 (depends on 4)

The shift register circuit of claim 4, wherein the first clock and the second clock have a skew difference there between.

### Claim 8

A memory device, comprising:
a nonvolatile memory circuit capable of storing repair data;
data buses capable of transferring the repair data outputted by the nonvolatile memory circuit;
a shift register circuit comprising first to Nth stages and sequentially activating output signals of the first to Nth stages whenever a clock is activated;
first to Nth storage circuits each capable of storing the repair data from the data buses in response to an activation of a corresponding output signal of the output signals of the first to Nth stages; and
a plurality of memory banks capable of being repaired using the repair data stored in the first to Nth storage circuits,
wherein each of the first to Nth stages comprises:
a D latch capable of latching an input signal in synchronization with the clock; and
a D flip-flop capable of latching an output signal of the D latch in synchronization with the clock, and
wherein the clock transferred to each of the first to Nth stages have a skew difference there between.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein:
the D latch latches the input signal when the clock has a logic low level; and
the D flip-flop latches the output signal of the D latch at a falling edge of the clock.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein:
the D latch latches the input signal when the clock has a logic high level; and
the D flip-flop latches the output signal of the D latch at a rising edge of the clock.

### Claim 11

A shift register circuit, comprising:
a first D latch capable of latching an input signal in synchronization with a clock;
a first D flip-flop capable of latching an output signal of the first latch in synchronization with the clock;
a second D latch capable of latching an output signal of the first flip-flop in synchronization with the clock; and
a second D flip-flop capable of latching an output signal of the second latch circuit in synchronization with the clock,
wherein the first D latch and the first D flip-flop have a delay difference due to having different paths in which they receive the clock from the second D latch and the second D flip-flop.

### Claim 12 (depends on 11)

The shift register circuit of claim 11, wherein:
the first and second D latches latch the input signal and output signal of the first D flip-flop, respectively, based on a logic level of the clock; and
the first and second D flip-flops latch the respective output signals of the first and second D latches based on an edge of the logic level of the clock.