# US 9,437,322 B2 · Circuit and method for reducing write disturb in a non-volatile memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,322 B2 - Document ID: US9437322B2 - Status: Granted - Kind: B2 - Application number: 15/055,972 - Filed: 2016-02-29 - Published: 2016-06-23 - Granted: 2016-09-06 - Earliest claimed: 2012-05-18 - Assignees: Sidense Corp. - Applicants: Sidense Corp. - Inventors: Steven Smith - Web page: https://patentgrep.com/patent/US9437322B2 ## CPC - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C 17/16: using electrically-fusible links - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An active precharge circuit for a non-volatile memory array which minimizes write disturb to non-selected memory cells during programming is disclosed. In a programming cycle, all bitlines are pre-charged to a program inhibit voltage level and held at the program inhibit voltage level with current or voltage sources coupled to each of the bitlines in a precharge operation and a following programming operation. In the programming operation, a bitline connected to a memory cell to be programmed is driven to a programming level, such as VSS, while the active precharge circuit is enabled to enable programming thereof. Because the other non-selected bitlines are held at the program inhibit voltage level, they will not be inadvertently programmed when the programming voltage is supplied by the word line. ## Claims ### Claim 1 A one-time programmable (OTP) memory comprising: OTP memory cells connected to bitlines and wordlines; a precharge circuit configured to maintain non-selected bitlines at a precharge voltage before executing a bitline access operation and configured to end maintaining the non-selected bitlines at the precharge voltage after commencement of the bitline access operation; and, access circuitry configured to execute the bitline access operation to access the memory cell connected to a selected bitline initially precharged to the precharge voltage. ### Claim 2 (depends on 1) The memory of claim 1, wherein the access circuitry includes a write circuit configured for driving the selected bitline to a voltage level for enabling programming of an OTP memory cell connected to the selected bitline when the selected wordline is driven to a programming voltage level. ### Claim 3 (depends on 2) The memory of claim 2, wherein the precharge voltage is a program inhibit voltage. ### Claim 4 (depends on 3) The OTP memory of claim 3, wherein the precharge circuit includes an active precharge current source receiving the program inhibit voltage connected to each of the bitlines, and configured to operate in a high current mode during a precharge operation prior to the programming operation, and to operate in the low current mode during the programming operation. ### Claim 5 (depends on 4) The OTP memory of claim 4, wherein the write circuit includes a sense amplifier for storing write data, the sense amplifier including discharge circuitry configured to overwrite the program inhibit voltage of the selected bitline. ### Claim 6 (depends on 3) The OTP memory of claim 3, wherein the precharge circuit is configured to operate in a high current mode during a precharge operation prior to the programming operation, and to operate in a low current mode during the programming operation in response to a controllable bias voltage. ### Claim 7 (depends on 6) The OTP memory of claim 6, further including a bias voltage generator configured to set the controllable bias voltage between a first voltage level in the high current mode and a second voltage level the low current mode, in response to an enable signal. ### Claim 8 (depends on 3) The OTP memory of claim 3, wherein the precharge circuit includes active precharge current sources receiving the program inhibit voltage, each being connected to one of the bitlines and configured to operate in a high current mode during a precharge operation prior to the programming operation, and to operate in a low current mode during the programming operation. ### Claim 9 (depends on 1) The OTP memory of claim 1, wherein the precharge circuit is connected to each bitline and includes a first transistor device receiving the precharge voltage in response to a controllable bias voltage, and a second transistor device for coupling the first transistor device to the bitline in response to a precharge signal. ### Claim 10 (depends on 9) The OTP memory of claim 9, further including a bias voltage generator configured to set the controllable bias voltage to a first voltage level in a high current mode and to a second voltage level in a low current mode, in response to an enable signal. ### Claim 11 (depends on 10) The OTP memory of claim 10, wherein the first voltage level is a first supply voltage, and the second voltage level is between the first supply voltage and a second supply voltage. ### Claim 12 (depends on 9) The OTP memory of claim 9, wherein the write circuit includes a sense amplifier for storing write data, the sense amplifier including discharge circuitry configured to overcome the first transistor device and the second transistor device operating in the low current mode. ### Claim 13 A one-time programmable (OTP) memory comprising: OTP memory cells connected to bitlines and wordlines; a precharge circuit configured to maintain selected and non-selected bitlines at a precharge voltage before executing a bitline access operation and configured to end maintaining the selected and non-selected bitlines at the precharge voltage after commencement of the bitline access operation; and, access circuitry configured to execute the bitline access operation to access the memory cell connected to a selected bitline initially precharged to the precharge voltage. ### Claim 14 (depends on 13) The OTP memory of claim 13, wherein the bitline access operation is a programming operation. ### Claim 15 (depends on 14) The OTP memory of claim 14, wherein the precharge circuit is configured to operate in a high current mode during a precharge operation prior to the programming operation, and to operate in a low current mode during the programming operation in response to a controllable bias voltage. ### Claim 16 (depends on 14) The OTP memory of claim 14, wherein the precharge circuit is configured to operate in a high current mode during a precharge operation prior to the programming operation for all the bitlines, and to operate in a low current mode during the programming operation for the selected bitline in response to a controllable bias voltage. ### Claim 17 A memory precharge circuit, comprising: an active precharge current source connected in series between a bitline connected to a memory cell and a precharge voltage, configured to provide high current to the bitline in response to a first bias voltage, and configured to provide low current to the bitline in response to a second bias voltage, the active precharge current source providing at least one of the high current and the low current during a bitline access operation. ### Claim 18 (depends on 17) The precharge circuit of claim 17, wherein the active precharge current source provides the high current to the bitline before activation of a wordline connected to the memory cell to precharge the bitline to the precharge voltage level. ### Claim 19 (depends on 18) The precharge circuit of claim 18, wherein the active precharge current source provides the low current to the bitline after the high current is provided and before activation of the wordline.