# US 9,437,317 B2 · Nonvolatile memory device, memory system having the same, external power controlling method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,317 B2 - Document ID: US9437317B2 - Status: Granted - Kind: B2 - Application number: 14/835,230 - Filed: 2015-08-25 - Published: 2015-12-17 - Granted: 2016-09-06 - Earliest claimed: 2013-01-18 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: TaeHyun Kim; June-Hong Park; Sungwhan Seo; Jinyub Lee - Web page: https://patentgrep.com/patent/US9437317B2 ## CPC - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/12: Programming voltage switching circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal. ## Claims ### Claim 1 A nonvolatile memory device comprising: an internal circuit; a first voltage pad configured to provide a first voltage to the internal circuit; a second voltage pad configured to provide a second voltage to the internal circuit, the second voltage being higher than the first voltage; and an external power control logic including, a first voltage detector configured to connect to the first voltage pad and the second voltage pad, and to generate a detection signal to switch between the second voltage pad and the internal circuit based on a voltage level of the first voltage; and a second voltage detector configured to generate a flag signal to protect the internal circuit based on a voltage level of the second voltage. ### Claim 2 (depends on 1) The nonvolatile memory device of claim 1, wherein the external power control logic further comprises: at least one switch connected between the second voltage pad and the internal circuit. ### Claim 3 (depends on 2) The nonvolatile memory device of claim 2, wherein the first voltage detector controls the at least one switch based on the detection signal. ### Claim 4 (depends on 2) The nonvolatile memory device of claim 2, wherein the second voltage detector controls the at least one switch based on the flag signal. ### Claim 5 (depends on 1) The nonvolatile memory device of claim 1, wherein the external power control logic further comprises: a first switch connected between the second voltage pad and a switched node; and a second switch connected between the switched node and the internal circuit. ### Claim 6 (depends on 5) The nonvolatile memory device of claim 5, wherein the second voltage detector is connected to the first voltage pad and the switched node. ### Claim 7 (depends on 6) The nonvolatile memory device of claim 6, wherein the first voltage detector is configured to control the first switch based on the detection signal. ### Claim 8 (depends on 6) The nonvolatile memory device of claim 6, wherein the second voltage detector is configured to control the second switch based on the flag signal. ### Claim 9 (depends on 6) The nonvolatile memory device of claim 6, wherein the first voltage detector is configured to transmit the detection signal to an output terminal associated therewith, and the first voltage detector comprises: a depletion transistor having a drain connected to the second voltage pad and a gate connected to the output terminal; a PMOS transistor having a drain connected to a source of the depletion transistor, a source connected to the output terminal, and a gate connected to the first voltage pad; and an NMOS transistor having a source connected to the output terminal, a drain grounded, and gate connected to the first voltage pad. ### Claim 10 (depends on 6) The nonvolatile memory device of claim 6, wherein the second voltage detector comprises: a voltage divider configured to divide a voltage of the switched node to generate a division voltage; and a comparator configured to output the flag signal if the division voltage is lower than a reference voltage. ### Claim 11 (depends on 10) The nonvolatile memory device of claim 10, wherein the internal circuit is configured to perform a recovery operation in response to the flag signal to discharge word lines and bit lines connected to a plurality of memory cells. ### Claim 12 A nonvolatile memory device comprising: an internal circuit; a first voltage pad configured to provide a first voltage to the internal circuit; a second voltage pad configured to provide a second voltage to the internal circuit, the second voltage being higher than the first voltage; and an external power control logic configured to, generate a detection signal based on a voltage level of the first voltage, the detection signal used to switch between the second voltage pad and the internal circuit, and generate a flag signal based on a voltage level of the second voltage, the external power control logic configured to protect the internal circuit based on the flag signal. ### Claim 13 (depends on 12) The nonvolatile memory device of claim 12, wherein the external power control logic is configured to activate the detection signal if the voltage level of the first voltage is lower than a voltage level to turn off a switch between the second voltage pad and the internal circuit. ### Claim 14 (depends on 12) The nonvolatile memory device of claim 12, wherein the external power control logic is configured to determine whether to apply the second voltage to the internal circuit based on the voltage level of the first voltage during a power-up operation. ### Claim 15 (depends on 14) The nonvolatile memory device of claim 14, wherein the external power control logic is configured to selectively apply the second voltage to a switched node between the second voltage pad and the internal circuit based on the detection signal. ### Claim 16 (depends on 12) The nonvolatile memory device of claim 12, wherein the external power control logic is configured to determine whether to apply the second voltage to the internal circuit based on the voltage level of the first voltage during a power-down operation. ### Claim 17 (depends on 16) The nonvolatile memory device of claim 16, wherein the external power control logic is configured to selectively apply the second voltage to a switched node between the second voltage pad and the internal circuit based on the detection signal. ### Claim 18 (depends on 17) The nonvolatile memory device of claim 17, wherein the external power control logic is configured to generate the flag signal based on a voltage level of the switched node and a reference voltage, the nonvolatile memory device configured to protect the internal circuit based on the flag signal. ### Claim 19 (depends on 17) The nonvolatile memory device of claim 17, wherein the external power control logic comprises: a first switch connected between the second voltage pad and the switched node; and a second switch connected between the switched node and the internal circuit, wherein the external power control logic is configured to generate the flag signal when a voltage level of the switched node is lower than a reference voltage, and to turn off the second switch in response to the flag signal. ### Claim 20 (depends on 19) The nonvolatile memory device of claim 19, wherein the external power control logic is configured to terminate a current mode of the nonvolatile memory device and set the nonvolatile memory device into a standby mode in response to the flag signal.