# US 9,437,313 B2 · Non-volatile memory device and related read method using adjustable bit line connection signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,313 B2 - Document ID: US9437313B2 - Status: Granted - Kind: B2 - Application number: 14/330,142 - Filed: 2014-07-14 - Published: 2014-10-30 - Granted: 2016-09-06 - Earliest claimed: 2011-02-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Eun-jin Yun; Sang-chul Kang - Web page: https://patentgrep.com/patent/US9437313B2 ## CPC - G11C 16/24: Bit-line control circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor. ## Claims ### Claim 1 A method of reading a non-volatile memory device comprising memory cells organized in blocks, each block comprising a plurality of pages, the memory cells being included in a cell string connected in series between at least one string selection transistor connected to a string select line and a ground selection transistor connected to a ground select line, and the cell string being connected to a page buffer via a bit line connection transistor that operates in response to a bit line connection signal, the method comprising: receiving a read instruction designating a selected page of a selected block of memory cells; applying, in response to the bit line connection signal, a precharge voltage to a bit line connected to the selected page, wherein the precharge voltage varies with the voltage level of the bit line connection signal; applying a read voltage to a word line connected to the selected page and applying a pass voltage to word lines connected to remaining non-selected pages; and reading the selected page, wherein a voltage level of the bit line connection signal is adjusted according to a distance between the word line of the selected page and a string select line connected to at least one string select transistor designating the selected block, such that the voltage level of the bit line connection signal is set high when the selected page is adjacent to the string selection line and is set low when the selected page is adjacent to the ground selection line. ### Claim 2 (depends on 1) The method of claim 1, further comprising: identifying a program/erase cycle for the selected block, wherein the voltage level of the bit line connection signal is further adjusted according to the program/erase cycle. ### Claim 3 (depends on 1) The method of claim 1, wherein the voltage level of the bit line connection signal corresponding to each of the plurality of pages gradually decreases by a predetermined value from the voltage level of the bit line connection signal of a page adjacent to the string selection line. ### Claim 4 (depends on 3) A method of claim 3 reading a non-volatile memory device comprising memory cells organized in blocks, each block comprising a plurality of pages, the memory cells being included in a cell string connected in series between at least one string selection transistor connected to a string select line and a ground selection transistor connected to a ground select line, and the cell string being connected to a page buffer via a bit line connection transistor that operates in response to a bit line connection signal, the method comprising: receiving a read instruction designating a selected page of a selected block of memory cells; applying, in response to the bit line connection signal, a precharge voltage to a bit line connected to the selected page, wherein the precharge voltage varies with the voltage level of the bit line connection signal; applying a read voltage to a word line connected to the selected page and applying a pass voltage to word lines connected to remaining non-selected pages; and reading the selected page, wherein a voltage level of the bit line connection signal is adjusted according to a distance between the word line of the selected page and a string select line connected to at least one string select transistor designating the selected block, the plurality of pages is divided into predetermined groups, and the voltage level of the bit line connection signal is set high when the selected page belongs to a group adjacent to the string selection line and is set low when the selected page belongs to a group adjacent to the ground selection line. ### Claim 5 (depends on 4) The method of claim 4, wherein the voltage level of the bit line connection signal corresponding to each of the predetermined groups gradually decreases by a predetermined value from the voltage level of the bit line connection signal in the group adjacent to the string selection line. ### Claim 6 (depends on 4) The method of claim 4, further comprising: identifying a program/erase cycle for the selected block, wherein the voltage level of the bit line connection signal is further adjusted according to the program/erase cycle. ### Claim 7 (depends on 4) The method of claim 4, wherein the voltage level of the bit line connection signal is set high when the selected page is adjacent to the string selection line and is set low when the selected page is adjacent to the ground selection line. ### Claim 8 A method of reading a non-volatile memory device, the non-volatile memory device comprising memory cells organized in blocks, each block comprising a plurality of pages, the memory cells being included in a cell string connected in series between at least one string selection transistor connected to a string select line and a ground selection transistor connected to a ground select line, the cell string being connected to a page buffer via a bit line connection transistor that operates in response to a bit line connection signal, and the method comprising: receiving a read instruction designating a selected page of a selected block of memory cells; applying a precharge voltage to a bit line connected to the selected page in response to the bit line connection signal, wherein the precharge voltage varies with the voltage level of the bit line connection signal; applying a read voltage to a word line connected to the selected page and applying a pass voltage to word lines connected to remaining non-selected pages; and reading the selected page, wherein a voltage level of the bit line connection signal of a selected memory cell located closest to the string selection transistor is set higher than a voltage level of the bit line connection signal for a selected memory cell located closest to the ground selection transistor. ### Claim 9 (depends on 8) The method of claim 8, further comprising: identifying a program/erase cycle for the selected block, wherein the voltage level of the bit line connection signal is further adjusted according to the program/erase cycle.