# US 9,437,309 B2 · Operating method of NAND flash memory unit

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- Number: US 9,437,309 B2
- Document ID: US9437309B2
- Status: Granted
- Kind: B2
- Application number: 14/943,035
- Filed: 2015-11-17
- Published: 2016-03-17
- Granted: 2016-09-06
- Earliest claimed: 2013-03-25
- Assignees: Phison Electronics Corp.
- Applicants: Phison Electronics Corp.
- Inventors: Wei Lin; Yu-Cheng Hsu; Kuo-Yi Cheng
- Web page: https://patentgrep.com/patent/US9437309B2

## CPC

- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

## Claims

### Claim 1

An operating method of a NAND flash memory unit, wherein the NAND flash memory unit comprises a plurality of gate layers, a conductive structure, and a charge trapping layer, wherein the conductive structure and the charge trapping layer penetrate the gate layers, wherein the charge trapping layer is disposed between the conductive structure and the gate layers, and wherein the operating method comprises:
applying an electric potential difference between a first end of the conductive structure and a second end of the conductive structure so as to generate a current in the conductive structure to heat up the charge trapping layer.

### Claim 2 (depends on 1)

The operating method according to claim 1, wherein a material of the conductive structure is doped poly-silicon.

### Claim 3 (depends on 2)

The operating method according to claim 2, wherein the step of applying the electric potential difference between the first end and the second end of the conductive structure further comprises:
applying an erasing voltage on the conductive structure.

### Claim 4 (depends on 3)

The operating method according to claim 3, wherein the NAND flash memory unit further comprises:
a first select gate layer, disposed on a side of the gate layers; and
a second select gate layer, disposed on another side of the gate layers, wherein the conductive structure and the charge trapping layer penetrate the first select gate layer and the second select gate layer,
wherein the operating method further comprises:
applying a base voltage to the gate layers; and
applying a third voltage to the first select gate layer and the second select gate layer, wherein a voltage level of the third voltage is generated based on a voltage level of the base voltage, a voltage level of the erasing voltage, and a voltage level of a tunneling voltage.

### Claim 5 (depends on 2)

The operating method according to claim 2, wherein the NAND flash memory unit further comprises a first select gate layer and a second select gate layer, wherein the first select gate layer is disposed on a side of the gate layers, wherein the second select gate layer is disposed on another side of the gate layers, wherein the conductive structure and the charge trapping layer penetrate the first select gate layer and the second select gate layer, and wherein the step of applying the electric potential difference between the first end and the second end of the conductive structure further comprises:
applying a system voltage to the first select gate layer and the second select gate layer; and
applying a passing voltage to the gate layers.

### Claim 6 (depends on 1)

The operating method according to claim 1, wherein a first dielectric layer is comprised between two adjacent gate layers among the gate layers, wherein the conductive structure comprises a tunnel layer, a conductor layer, and a second dielectric layer, wherein the second dielectric layer is disposed between the tunnel layer and the conductor layer, and wherein the first end and the second end of the conductive structure is between a first end and a second end of the conductor layer,
wherein the NAND flash memory unit further comprises:
a first select gate layer, disposed on a side of the gate layers; and
a second select gate layer, disposed on another side of the gate layers, wherein the tunnel layer, the conductor layer, the second dielectric layer, and the charge trapping layer penetrate the first select gate layer and the second select gate layer.

### Claim 7 (depends on 6)

The operating method according to claim 6 further comprising:
applying an erasing voltage to an end of the tunnel layer;
applying a base voltage to the gate layers; and
applying a third voltage to the first select gate layer and the second select gate layer, wherein a voltage level of the third voltage is generated based on a voltage level of the base voltage, a voltage level of the erasing voltage, and a voltage level of a tunneling voltage.

### Claim 8 (depends on 7)

The operating method according to claim 7, wherein voltage levels at the first end and the second end of the conductor layer is generated based on the voltage level of the base voltage, the voltage level of the erasing voltage, and a voltage level of an offset voltage, and wherein the electric potential difference exists between the first end and the second end of the conductor layer.

### Claim 9 (depends on 6)

The operating method according to claim 6 further comprising:
floating the gate layers, the first select gate layers, the second select gate layer, a first end of the tunnel layer and a second end of the tunnel layer.

### Claim 10 (depends on 6)

The operating method according to claim 6 further comprising:
setting voltage levels at the first end and the second end of the conductor layer as input parameters of a function, wherein the function outputs a value, and wherein the value is between the voltage levels at the first end and the second end of the conductor layer; and
applying a voltage with the value to the gate layers, the first select gate layer, the second select gate layer, a first end of the tunnel layer, and a second end of the tunnel layer.

### Claim 11 (depends on 6)

The operating method according to claim 6, wherein a material of the conductor layer comprises a metal.

### Claim 12 (depends on 6)

The operating method according to claim 6, wherein a material of the conductor layer comprises doped poly-silicon.