# US 9,437,301 B2 · Non-volatile semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,301 B2 - Document ID: US9437301B2 - Status: Granted - Kind: B2 - Application number: 14/669,407 - Filed: 2015-03-26 - Published: 2015-07-16 - Granted: 2016-09-06 - Earliest claimed: 2011-01-13 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Masanobu Shirakawa - Web page: https://patentgrep.com/patent/US9437301B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 29/025: {in signal lines} - G11C 29/50004: {of threshold voltage} - G11C 29/789: {using non-volatile cells or latches} - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 16/00: Erasable programmable read-only memories (G11C14/00 takes precedence) - G11C 16/02: electrically programmable - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} - G11C 2029/1202: {Word line control} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region. ## Claims ### Claim 1 A memory device comprising: a memory cell array including a plurality of blocks, one of the blocks being a unit of an erase operation, the blocks including a first block, the first block including a plurality of memory cells stacked in a first direction crossing a semiconductor substrate, the first block including a plurality of pages, one of the pages being a unit of a read operation or a write operation, the pages including a first page and a second page; and a controller configured to execute a read operation for the first page when the controller receives an address corresponding to the first page, the controller being configured not to execute a read operation for the second page when the controller receives an address corresponding to the second page and the second page is defective. ### Claim 2 (depends on 1) The memory device according to claim 1, wherein the memory cell array is composed of a plurality of memory strings, one of the memory strings including a plurality of memory cells connected in series, a first select transistor, and a second select transistor, the memory cells being disposed between the first select transistor and the second select transistor. ### Claim 3 (depends on 1) The memory device according to claim 1, wherein a first data whether the first page is defective is stored in the memory cell array. ### Claim 4 (depends on 3) The memory device according to claim 3, wherein a second data whether the second page is defective is stored in the memory cell array. ### Claim 5 (depends on 3) The memory device according to claim 3, wherein the first data includes a plurality of block addresses and a plurality of logical block addresses. ### Claim 6 A memory device comprising: a memory cell array including a plurality of blocks, one of the blocks being a unit of an erase operation, the blocks including a first block, the first block including a plurality of word lines stacked in a first direction crossing a semiconductor substrate, the plurality of word lines including a first word line and a second word line, one of a plurality of memory cells being electrically connected to one of the word lines; and a controller configured to execute a read operation for a memory cell electrically connected to the first word line when the controller receives address corresponding to the first word line, the controller being configured not to execute a read operation for a memory cell electrically connected to the second word line when the controller receives address corresponding to the second word line and the second word line is defective. ### Claim 7 (depends on 6) The memory device according to claim 6, wherein the memory cell array is composed of a plurality of memory strings, one of the memory strings including a plurality of memory cells connected in series, a first select transistor, and a second select transistor, the memory cells being disposed between the first select transistor and the second select transistor. ### Claim 8 (depends on 6) The memory device according to claim 6, wherein a first data whether the first word line is defective is stored in the memory cell array. ### Claim 9 (depends on 8) The memory device according to claim 8, wherein a second data whether the second word line is defective is stored in the memory cell array. ### Claim 10 (depends on 8) The memory device according to claim 8, wherein the first data includes a plurality of block addresses and a plurality of logical block addresses.