# US 9,437,300 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,300 B2 - Document ID: US9437300B2 - Status: Granted - Kind: B2 - Application number: 14/469,251 - Filed: 2014-08-26 - Published: 2015-09-17 - Granted: 2016-09-06 - Earliest claimed: 2014-03-14 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Hideyuki Kamata; Toshifumi Minami; Teppei Higashitsuji; Atsuhiro Sato; Keisuke Yonehama; Yasuyuki Baba; Hiroshi Shinohara - Web page: https://patentgrep.com/patent/US9437300B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/12: Programming voltage switching circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different. ## Claims ### Claim 1 A semiconductor memory device comprising: a first memory cell transistor stacked above a semiconductor substrate; a second memory cell transistor stacked above the first memory cell transistor; first and second word lines electrically connected to gates of the first and second memory cell transistors, respectively; and a first transfer transistor electrically connected to the first word line and a second transfer transistor electrically connected to the second word line, wherein sizes of the first and second transfer transistors are different. ### Claim 2 (depends on 1) The device according to claim 1, wherein either or both of respective gate lengths and gate widths of the first and second transfer transistors are different. ### Claim 3 (depends on 1) The device according to claim 1, wherein a size of the first memory cell transistor is smaller than a size of the second memory cell transistor, and the size of the first transfer transistor is smaller than the size of the second transfer transistor. ### Claim 4 (depends on 1) The device according to claim 1, wherein a size of the first memory cell transistor is larger than a size of the second memory cell transistor, and the size of the first transfer transistor is larger than the size of the second transfer transistor. ### Claim 5 (depends on 1) The device according to claim 1, further comprising: a third memory cell transistor stacked above the second memory cell transistor; a third word line electrically connected to a gate of the third memory cell transistor; and a third transfer transistor electrically connected to the third word line, wherein a size of the second memory cell transistor is smaller than a size of the third memory cell transistor, and sizes of the second and third transfer transistors are the same. ### Claim 6 (depends on 1) The device according to claim 1, further comprising: a bit line and a source line between which the first and second memory cell transistors are electrically connected in series, wherein the bit line is farther from the semiconductor substrate than the first and second memory cell transistors, and the source line is farther from the semiconductor substrate than the first and second memory cell transistors. ### Claim 7 (depends on 1) The device according to claim 1, further comprising: a bit line and a source line between which the first and second memory cell transistors are electrically connected in series, wherein the bit line is farther from the semiconductor substrate than the first and second memory cell transistors, and the source line is closer to the semiconductor substrate than the first and second memory cell transistors. ### Claim 8 A semiconductor memory device comprising: a plurality of memory cell transistors that are stacked above a semiconductor substrate, the memory cell transistors having sizes that increase in proportion to a distance thereof to the semiconductor substrate; a plurality of word lines, each of which is electrically connected to a gate of one of the memory cell transistors; a plurality of word line driver circuits, each of which is configured to generate a voltage for one of the word lines; and a plurality of transistors, each of which is electrically connected at a first end to one of the word line driver circuits and at a second end to one of the word lines, the transistors having sizes that increase in proportion to a distance of the memory cell transistor electrically connected thereto to the semiconductor substrate. ### Claim 9 (depends on 8) The device according to claim 8, wherein the word lines are stacked above the semiconductor substrate, and a semiconductor column extends through the word lines and a charge storage layer for the memory cell transistors is interposed between the semiconductor column and the word lines, sizes of the semiconductor column at intersections with the word lines increasing in proportion to a distance thereof to the semiconductor substrate. ### Claim 10 (depends on 9) The device according to claim 9, wherein the semiconductor column has a substantially circular cross-section at each of the intersections with the word lines and diameters of the semiconductor column at intersections with the word lines increasing in proportion to the distance thereof to the semiconductor substrate. ### Claim 11 (depends on 8) The device according to claim 8, further comprising: a bit line and a source line between which the memory cell transistors are electrically connected in series, wherein the bit line is farther from the semiconductor substrate than the memory cell transistors, and the source line is farther from the semiconductor substrate than the memory cell transistors. ### Claim 12 (depends on 8) The device according to claim 8, further comprising: a bit line and a source line between which the memory cell transistors are electrically connected in series, wherein the bit line is farther from the semiconductor substrate than the memory cell transistors, and the source line is closer to the semiconductor substrate than the memory cell transistors. ### Claim 13 (depends on 8) The device according to claim 8, wherein respective gate lengths of the transistors are different. ### Claim 14 (depends on 8) The device according to claim 8, wherein respective gate widths of the transistors are different. ### Claim 15 A semiconductor memory device comprising: a plurality of memory cell transistors stacked above a semiconductor substrate, a first group of M memory cell transistors being closer to the semiconductor substrate than a second group of N memory cell transistors, where M and N are both greater than 1, a plurality of word lines including a first word line electrically connected to a gate of one of the memory cell transistors in the first group and a second word line electrically connected to a gate of one of the memory cell transistors in the second group; and a row decoder including a first transfer transistor electrically connected to the first word line and a second transfer transistor electrically connected to the second word line, wherein sizes of the first and second transfer transistors are different. ### Claim 16 (depends on 15) The device according to claim 15, wherein M is equal to N. ### Claim 17 (depends on 15) The device according to claim 15, wherein M is not equal to N. ### Claim 18 (depends on 15) The device according to claim 15, wherein either or both of respective gate lengths and gate widths of the first and second transfer transistors are different. ### Claim 19 (depends on 15) The device according to claim 15, wherein the size of the first transfer transistor is smaller than the size of the second transfer transistor. ### Claim 20 (depends on 15) The device according to claim 15, wherein the size of the first transfer transistor is larger than the size of the second transfer transistor.