# US 9,437,298 B1 · Self-storing and self-restoring non-volatile static random access memory

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- Number: US 9,437,298 B1
- Document ID: US9437298B1
- Status: Granted
- Kind: B1
- Application number: 14/668,896
- Filed: 2015-03-25
- Published: 2016-09-29
- Granted: 2016-09-06
- Earliest claimed: 2015-03-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shigeki Tomishima; Dmitri E. Nikonov; Elijah V. Ilya Karpov; Ian A. Young; Robert S. Chau
- Web page: https://patentgrep.com/patent/US9437298B1

## CPC

- G11C 14/009: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C 11/416: Read-write [R-W] circuits
- G11C 11/419: Read-write [R-W] circuits
- G11C 11/4116: {with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL}
- G11C 11/412: using field-effect transistors only
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.

## Claims

### Claim 1

An apparatus comprising:
a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and
first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements, wherein the first logic is to self-store the data by discharging voltages on both a bit-line and a complementary bit-line to ground.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first logic is operable to self-store the data when the voltage applied to the SRAM cell decreases to a threshold voltage or gets close to the threshold voltage.

### Claim 3 (depends on 1)

The apparatus of claim 1 comprises second logic to self-restore data from the at least two NV resistive memory elements back to the SRAM cell.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the second logic is operable to self-restore data from the at least two NV resistive memory elements when the voltage applied to the SRAM cell increases to a threshold voltage.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the second logic is operable to self-restore data from the at least two NV resistive memory elements when the voltage applied to the SRAM cell is close to a power supply level.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the second logic is operable to apply ground voltages to the bit-line, complementary bit-line, and a word-line during power-up.

### Claim 7 (depends on 1)

The apparatus of claim 1 comprises third logic which is operable to reset the at least two NV resistive memory elements.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the third logic is operable to reset the at least two NV resistive memory elements by setting bit-line and complementary bit-line to logic high.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the at least two NV resistive elements are coupled in series.

### Claim 10 (depends on 9)

The apparatus of claim 9, comprises a source transistor coupled to a common node of the at least two NV resistive elements.

### Claim 11 (depends on 10)

The apparatus of claim 10 comprises logic to bypass the at least two NV resistive elements during normal memory operation.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the logic causes current to flow from bit-line and complementary bit-line through the at least two NV resistive elements and the source transistor.

### Claim 13 (depends on 9)

The apparatus of claim 9 comprises:
a first transistor coupled to one of the at least two NV resistive elements and a first access device; and
a second transistor coupled to another of the at least two NV resistive elements and a second access device.

### Claim 14 (depends on 13)

The apparatus of claim 13 comprises:
a third transistor coupled to a common node of the first transistor and the one of the at least two NV resistive elements; and
a fourth transistor coupled to a common node of the second transistor and the other of the at least two NV resistive elements.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the second and fourth transistors are controllable by a second control signal.

### Claim 16 (depends on 13)

The apparatus of claim 13, wherein the first and third transistors are controllable by a first control signal.

### Claim 17 (depends on 1)

The apparatus of claim 1, wherein the NV resistive memory elements are integrated with the SRAM cell such that states of the NV resistive memory elements are preserved during normal operations of the SRAM cell.

### Claim 18

A system comprising:
a processor;
a memory coupled to the processor, the memory including:
a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and
first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements, wherein the first logic is to self-store the data by discharging voltages on both a bit-line and a complementary bit-line to ground; and
a wireless interface for allowing the processor to communicate with another device.

### Claim 19 (depends on 18)

The system of claim 18, wherein the first logic is operable to self-store the data when a memory having the SRAM cell is being powered down, and wherein the memory comprises second logic to self-restore data from the at least two NV resistive memory elements back to the SRAM cell.

### Claim 20

A method comprising:
performing a self-storing operation, when a voltage applied to a Static Random Access Memory (SRAM) cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two non-volatile (NV) resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and
performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell, wherein performing the self-storing operation comprises setting bit-line and complementary bit-line associated with the SRAM cell to ground.

### Claim 21 (depends on 20)

The method of claim 20 comprises performing reset operation on the at least two NV resistive memory elements.

### Claim 22 (depends on 21)

The method of claim 21, wherein performing the reset operation comprises setting bit-line and complementary bit-line to logic high.

### Claim 23 (depends on 20)

The method of claim 20, wherein the NV resistive memory elements are integrated with the SRAM cell such that states of the NV resistive memory elements are preserved during normal operations of the SRAM cell.