# US 9,437,293 B1 · Integrated setback read with reduced snapback disturb > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,293 B1 - Document ID: US9437293B1 - Status: Granted - Kind: B1 - Application number: 14/671,471 - Filed: 2015-03-27 - Published: 2016-09-29 - Granted: 2016-09-06 - Earliest claimed: 2015-03-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Arjun Kripanidhi; Kiran Pangal; Lark-Hoon Leem; Balaji Srinivasan - Web page: https://patentgrep.com/patent/US9437293B1 ## CPC - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0064: {Verifying circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/0047: {Read destroying or disturbing the data} - G11C 2013/0052: {Read process characterized by the shape, e.g. form, length, amplitude of the read pulse} - G11C 2013/0066: {Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed. ## Claims ### Claim 1 An apparatus comprising: read circuitry, to apply a read voltage to a phase change memory (PCM) cell; setback circuitry coupled to the read circuitry, to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and sense circuitry coupled to the setback circuitry, to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first period of time is 1/100th of the second period of time or greater. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first period of time is 1/20th of the second period of time or less. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the setback circuitry is to apply the setback pulse to the PCM cell based on the PCM cell turning on in response to application of the read voltage. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the PCM cell is in the crystalline state and wherein the sense circuitry is to sense whether the PCM cell is in the amorphous state or the crystalline state subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the PCM cell is in the crystalline state and wherein the setback circuitry is to perform the setback pulse subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off. ### Claim 7 (depends on 1) The apparatus of claim 1, further comprising: current-limiting circuitry to limit or control a setback current through the PCM cell when the setback pulse is performed. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising: a transistor coupled with the PCM cell to reduce or isolate capacitance discharge from disturbing the PCM cell when the PCM cell turns on in response to application of the read voltage. ### Claim 9 A method comprising: applying a read voltage to a phase change memory (PCM) cell; applying a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and sensing, concurrently with applying the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. ### Claim 10 (depends on 9) The method of claim 9, wherein the first period of time is 1/100th of the second period of time or greater. ### Claim 11 (depends on 10) The method of claim 10, wherein the first period of time is 1/20th of the second period of time or less. ### Claim 12 (depends on 9) The method of claim 9, wherein applying the setback pulse to the PCM cell is performed in response to the PCM cell turning on based on application of the read voltage. ### Claim 13 (depends on 12) The method of claim 12, wherein the PCM cell is in the crystalline state and wherein the sensing is performed subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off. ### Claim 14 (depends on 9) The method of claim 9, wherein the PCM cell is in the crystalline state and wherein the setback pulse is applied subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off. ### Claim 15 (depends on 9) The method of claim 9, further comprising: limiting or controlling a setback current through the PCM cell when the setback pulse is performed. ### Claim 16 A non-transitory computer-readable medium having instructions stored thereon, the instructions when executed by a processor cause circuitry to: apply a read voltage to a phase change memory (PCM) cell; apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the first period of time is 1/100th of the second period of time or greater. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the first period of time is 1/20th of the second period of time or less. ### Claim 19 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the instructions when executed by a processor further cause circuitry to: apply the setback pulse during application of the read voltage. ### Claim 20 A computing device comprising: a circuit board; and a die coupled with the circuit board, the die including read circuitry to apply a read voltage to a phase change memory (PCM) cell; setback circuitry coupled to the read circuitry, to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and sense circuitry coupled to the setback circuitry, to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. ### Claim 21 (depends on 20) The computing device of claim 20, wherein the computing device is a mobile computing device.