# US 9,437,292 B1 · Circuits and methods for limiting current in random access memory cells

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,437,292 B1
- Document ID: US9437292B1
- Status: Granted
- Kind: B1
- Application number: 14/621,488
- Filed: 2015-02-13
- Published: 2016-08-18
- Granted: 2016-09-06
- Earliest claimed: 2015-02-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Yi-Chun Shih; Chung-Cheng Chou; Po-Hao Lee
- Web page: https://patentgrep.com/patent/US9437292B1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0038: {Power supply circuits}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2013/0066: {Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.

## Claims

### Claim 1

A memory cell, comprising:
a first low dropout regulator (LDO) comprising a first operational amplifier and a first PMOS transistor arranged in a closed loop, a first input of the first operational amplifier receiving a reference voltage VREF, an output of the first operational amplifier being coupled to a gate of the first PMOS transistor, and a drain of the first PMOS transistor being coupled to a second input of the first operational amplifier, the first operational amplifier outputting gate voltage Vg to the gate of the first PMOS transistor based upon a value of reference voltage VREF, the first LDO outputting bit line voltage VBL;
a resistive random access memory (RRAM) cell coupled to the first LDO, the RRAM cell comprising a first select transistor and a programmable resistor, a gate of the first select transistor being coupled to a word line and receiving a word line voltage VWL, a drain of the first select transistor being coupled to a ground, the RRAM cell receiving as input the bit line voltage VBL from the first LDO, the programmable resistor being configured to change between a relatively high resistance and a relatively low resistance responsive to changes in a cell current ICELL through the RRAM cell based upon values of VBL and VWL; and
a current limiter comprising a second PMOS transistor, a source of the second PMOS transistor being coupled to an input voltage VIN, a gate of the second PMOS transistor receiving a limit voltage Vplim, a drain of the second PMOS transistor being coupled to the first LDO.

### Claim 2 (depends on 1)

The memory cell of claim 1, the current limiter limiting a current provided to the source of the first PMOS transistor to a value ILIMIT.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein based upon ICELL being less than ILIMIT and the programmable resistor having the relatively high resistance, a voltage across the programmable resistor is substantially constant.

### Claim 4 (depends on 3)

The memory cell of claim 3, wherein based upon ICELL approaching or equaling ILIMIT responsive to the programmable resistor changing from the relatively high resistance to the relatively low resistance, a voltage across the second PMOS transistor increases, and
based upon the voltage across the second PMOS transistor increasing, ICELL decreases to a level that reduces or inhibits a further decrease in the resistance of the programmable resistor.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein the programmable resistor is coupled between the first PMOS transistor and the first select transistor.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the first select transistor is coupled between the programmable resistor and the first PMOS transistor.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein the first select transistor comprises an NMOS transistor.

### Claim 8 (depends on 1)

The memory cell of claim 1, further comprising a write throttle circuit, the write throttle circuit comprising an inverter and a flip-flop, the inverter including an input coupled to the output of the first operational amplifier and an output coupled to a reset input R of the flip-flop, a set input S of the flip-flop receiving a write voltage ThrottleENB, an output QB of the flip-flop being coupled to a third input of the operational amplifier,
wherein the inverter is configured to output a transition signal to the reset input R of the flip flop based upon Vg becoming lower than a threshold Vth,n based upon the programmable resistor changing to the relatively low resistance,
the flip-flop outputting an LDO disable signal LDODisable to the first operational amplifier responsive to the transition signal from the inverter and based upon write voltage ThrottleENB being high,
the output of the first operational amplifier disabling current flow through the gate of the first PMOS transistor responsive to the LDODisable signal.

### Claim 9 (depends on 8)

The memory cell of claim 8, wherein the inverter comprises a low-skewed inverter.

### Claim 10 (depends on 8)

The memory cell of claim 8, further comprising a delay circuit coupled between the output of the flip-flop and the third input of the first operational amplifier, the delay circuit configured to delay transmission of LDODisable to the third input of the first operational amplifier by a preselected amount of time.

### Claim 11 (depends on 10)

The memory cell of claim 10, wherein the delay circuit comprises a plurality of inverters connected in series with one another.

### Claim 12 (depends on 1)

The memory cell of claim 1, further comprising a reference cell coupled to the gate of the second PMOS transistor, the reference cell comprising:
a second LDO comprising a second operational amplifier and a third PMOS transistor arranged in a closed loop, a first input of the second operational amplifier receiving the reference voltage VREF, an output of the second operational amplifier being coupled to a gate of the third PMOS transistor, and a drain of the third PMOS transistor being coupled to a second input of the second operational amplifier, the second operational amplifier outputting reference gate voltage Vg,REF to the gate of the third PMOS transistor based upon a value of reference voltage VREF, the second LDO outputting reference bit line voltage VBL,REF;
a dummy cell coupled to the second LDO, the dummy cell comprising a second select transistor and a resistor having a fixed resistance, a gate of the second select transistor being coupled to the word line and receiving the word line voltage VWL, a drain of the second select transistor being coupled to the ground, the dummy cell receiving as input the reference bit line voltage VBL,REF from the second LDO, a current IREF through the dummy cell being based upon the fixed resistance and on the values of VBL,REF and VWL; and
a mirror current limiter comprising a fourth PMOS transistor, a source of the fourth PMOS transistor being coupled to the input voltage VIN, a gate of the fourth PMOS transistor being coupled to the gate of the second PMOS transistor, a drain of the fourth PMOS transistor being coupled to the second LDO and to the gate of the second and fourth PMOS transistors,
wherein the value of Vplim is based upon a difference between the resistance of the programmable resistor and the fixed resistance.

### Claim 13 (depends on 12)

The memory cell of claim 12, further comprising a bit line resistor having resistance RBL coupled between the RRAM cell and the first LDO and a select line resistor having resistance RSL coupled between the first select transistor and the ground,
the reference cell further comprising a reference bit line resistor having a reference resistance RBL,REF coupled between the dummy cell and the second LDO, and a reference select line resistor having resistance RSL,REF coupled between the second select transistor and the ground.

### Claim 14 (depends on 12)

The memory cell of claim 12, further comprising a write throttle circuit, the write throttle circuit comprising an inverter and a flip-flop, the inverter including an input coupled to the output of the first operational amplifier and an output coupled to a reset input R of the flip-flop, a set input S of the flip-flop receiving a write voltage ThrottleENB, an output QB of the flip-flop being coupled to a third input of the operational amplifier,
wherein the inverter is configured to output a transition signal to the reset input R of the flip flop based upon Vg becoming lower than a threshold Vth,n based upon the programmable resistor changing to the relatively low resistance,
the flip-flop outputting an LDO disable signal LDODisable to the first operational amplifier responsive to the transition signal from the inverter and based upon write voltage ThrottleENB being high,
the output of the first operational amplifier disabling current flow through the gate of the first PMOS transistor responsive to the LDODisable signal.

### Claim 15

A memory cell array, comprising:
a first low dropout regulator (LDO) comprising a first operational amplifier and a first PMOS transistor arranged in a closed loop, a first input of the first operational amplifier receiving a reference voltage VREF, an output of the first operational amplifier being coupled to a gate of the first PMOS transistor, and a drain of the first PMOS transistor being coupled to a second input of the first operational amplifier, the first operational amplifier outputting gate voltage Vg to the gate of the first PMOS transistor based upon a value of reference voltage VREF, the first LDO outputting bit line voltage VBL;
a current limiter comprising a second PMOS transistor, a source of the second PMOS transistor being coupled to an input voltage VIN, a gate of the second PMOS transistor receiving a limit voltage Vplim, a drain of the second PMOS transistor being coupled to the first LDO;
a plurality of memory cells, each memory cell of the plurality of memory cells comprising:
a resistive random access memory (RRAM) cell coupled to the first LDO, the RRAM cell comprising a first select transistor and a programmable resistor, a gate of the first select transistor being coupled to a word line and receiving a word line voltage VWL, the RRAM cell receiving as input the bit line voltage VBL from the first LDO, the programmable resistor being configured to change between a relatively high resistance and a relatively low resistance responsive to changes in a cell current ICELL through the RRAM cell based upon values of VBL and VWL; and
a reference cell coupled to the gate of the second PMOS transistor of each of the memory cells, the reference cell comprising:
a second LDO comprising a second operational amplifier and a third PMOS transistor arranged in a closed loop, a first input of the second operational amplifier receiving the reference voltage VREF, an output of the second operational amplifier being coupled to a gate of the third PMOS transistor, and a drain of the third PMOS transistor being coupled to a second input of the second operational amplifier, the second operational amplifier outputting reference gate voltage Vg,REF to the gate of the third PMOS transistor based upon a value of reference voltage VREF, the second LDO outputting reference bit line voltage VBL,REF;
a dummy cell coupled to the second LDO, the dummy cell comprising a second select transistor and a resistor having a fixed resistance, a gate of the second select transistor being coupled to the word line and receiving the word line voltage VWL, the dummy cell receiving as input the reference bit line voltage VBL,REF from the second LDO, a current IREF through the dummy cell being based upon the fixed resistance and on the values of VBL,REF and VWL; and
a mirror current limiter comprising a fourth PMOS transistor, a source of the fourth PMOS transistor being coupled to the input voltage VIN, a gate of the fourth PMOS transistor being coupled to the gate of the second PMOS transistor, a drain of the fourth PMOS transistor being coupled to the second LDO,
wherein the value of Vplim for each memory cell is based upon a difference between the resistance of the programmable resistor of that memory cell and the fixed resistance.

### Claim 16 (depends on 15)

The memory cell array of claim 15, each memory cell further comprising a bit line resistor having resistance RBL coupled between the RRAM cell and the first LDO and a select line resistor having resistance RSL coupled between the first select transistor and the ground,
the reference cell further comprising a reference bit line resistor having a reference resistance RBL,REF coupled between the dummy cell and the second LDO and a reference select line resistor having resistance RSL,REF coupled between the second select transistor and the ground.

### Claim 17 (depends on 15)

The memory cell array of claim 15, further comprising a plurality of write throttle circuits, each write throttle circuit being coupled to a corresponding one of the memory cells,
each write throttle circuit comprising an inverter and a flip-flop, the inverter including an input coupled to the output of the first operational amplifier of the corresponding memory cell and an output coupled to a reset input R of the flip-flop, a set input S of the flip-flop receiving a write voltage ThrottleENB, an output QB of the flip-flop being coupled to a third input of the operational amplifier of the corresponding memory cell,
wherein the inverter is configured to output a transition signal to the reset input R of the flip flop based upon Vg becoming lower than a threshold Vth,n based upon the programmable resistor of the corresponding memory cell changing to the relatively low resistance,
the flip-flop outputting an LDO disable signal LDODisable to the first operational amplifier of the corresponding memory cell responsive to the transition signal from the inverter and based upon write voltage ThrottleENB being high,
the output of the first operational amplifier of the corresponding memory cell disabling current flow through the gate of the first PMOS transistor of that memory cell responsive to the LDODisable signal.

### Claim 18 (depends on 15)

The memory cell array of claim 15, the current limiter of each memory cell limiting a current provided the source of the first PMOS transistor of that memory cell to a value ILIMIT,
optionally wherein based upon ICELL of that memory cell being less than ILIMIT and the programmable resistor of that memory cell having the relatively high resistance, a voltage across the programmable resistor is substantially constant, and
and further optionally wherein based upon ICELL of that memory cell approaching or equaling ILIMIT responsive to the programmable resistor of that memory cell changing from the relatively high resistance to the relatively low resistance, a voltage across the second PMOS transistor of that memory cell increases, and
based upon the voltage across the second PMOS transistor of that memory cell increasing, ICELL decreases to a level that reduces or inhibits a further decrease in the resistance of the programmable resistor of that memory cell.

### Claim 19

A method, comprising:
outputting a bit line voltage VBL with a low dropout regulator (LDO);
at a resistive random access memory (RRAM) cell coupled to the LDO, receiving as input the bit line voltage VBL from the LDO;
at a gate of a select transistor of the RRAM cell, receiving as input a word line voltage VWL;
at a programmable resistor of the RRAM cell, changing between a relatively high resistance and a relatively low resistance responsive to changes in a cell current ICELL through the RRAM cell based upon values of VBL and VWL; and
limiting current through the RRAM cell with a current limiter comprising a PMOS transistor, a gate of the PMOS transistor receiving a limit voltage Vpiini, a drain of the PMOS transistor being coupled to the LDO.

### Claim 20 (depends on 19)

The method of claim 19, wherein based upon ICELL being less than ILIMIT and the programmable resistor having the relatively high resistance, a voltage across the programmable resistor is substantially constant.