# US 9,437,290 B2 · Resistive memory device and operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,290 B2 - Document ID: US9437290B2 - Status: Granted - Kind: B2 - Application number: 14/631,182 - Filed: 2015-02-25 - Published: 2016-01-28 - Granted: 2016-09-06 - Earliest claimed: 2014-07-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Yong-Kyu Lee; Dae-Seok Byeon; Hyo-Jin Kwon; Hyun-Kook Park; Chi-Weon Yoon; Yeong-Taek Lee - Web page: https://patentgrep.com/patent/US9437290B2 ## CPC - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 11/5607: {using magnetic storage elements} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level. ## Claims ### Claim 1 A method of operating a resistive memory device, the method comprising: determining whether to perform a refresh operation on memory cells in a memory cell array; determining a respective resistance state of each of the memory cells, when the refresh operation is determined to be performed; classifying the memory cells within the memory cell array as first memory cells having a resistance state that is equal to or less than a critical resistance level and second memory cells having a resistance state that is greater than the critical resistance level; and performing a re-writing operation on the first memory cells among the memory cells. ### Claim 2 (depends on 1) The method of claim 1, wherein the re-writing operation comprises a set writing operation but not a reset writing operation. ### Claim 3 (depends on 1) The method of claim 1, wherein the re-writing operation comprises applying a current pulse to each of the first memory cells. ### Claim 4 (depends on 1) The method of claim 1, wherein the first memory cells have a resistance state other than an uppermost resistance state from among a plurality of resistance states. ### Claim 5 (depends on 1) The method of claim 1, further comprising performing a pre-reading operation on some of the memory cells. ### Claim 6 (depends on 1) The method of claim 1, further comprising: writing data to the first memory cells through a set writing operation; and writing data to the second memory cells through a reset writing operation. ### Claim 7 (depends on 1) The method of claim 1, wherein when the data is written in the memory cells, a bias voltage is applied to each of the first memory cells so that a filament is generated in a variable resistance device in the first memory cell, and a bias voltage is applied to each of the second memory cells so that a filament in a variable resistance device in the second memory cell is cut. ### Claim 8 (depends on 1) The method of claim 1, wherein the refresh operation is determined to be performed when a first reference time that is set in advance has passed after writing data in the memory cells. ### Claim 9 (depends on 1) The method of claim 1, wherein the determining of whether to perform the refresh operation comprises: increasing a counting value representing a number of reading operations, when receiving a read command; and determining whether the counting value has reached a reference value, wherein if the counting value reaches the reference value, it is determined to perform the refresh operation. ### Claim 10 (depends on 1) The method of claim 1, wherein the determining of whether to perform the refresh operation comprises: reading data written in the memory cells; performing error detection with respect to the read data; and determining whether a number of detected errors in the read data exceeds a reference value that is set in advance, wherein if the number of detected errors exceeds the reference value, it is determined to perform the refresh operation. ### Claim 11 (depends on 1) The method of claim 1, wherein the memory cell array comprises a plurality of cell regions, and the performing of the re-writing operation is performed by a cell region unit. ### Claim 12 A method of operating a resistive memory device comprising a plurality of memory cells each having a respective resistance state that is one of a plurality of resistance states including first and second groups of one or more resistance states, the first group of resistance states having a higher resistance level than the second group of resistance states, the method comprising: reading the resistance states of the plurality of memory cells; and re-writing the read resistance states to the plurality of memory cells, wherein a frequency of performing the re-writing on those of the memory cells having resistance states of the first group of resistance states is less than a frequency of performing the re-writing on those of the memory cells having resistance states of the second group of resistance states. ### Claim 13 (depends on 12) The method of claim 12, wherein the plurality of resistance states comprises a first resistance state having a first resistance level and a second resistance state having a second resistance level lower than the first resistance level, and the re-writing is performed on a memory cell having a third resistance state having a third resistance level that is between the first and second resistance levels. ### Claim 14 (depends on 12) The method of claim 12, wherein the re-writing is not performed on a memory cell having an uppermost resistance state of the plurality of resistance states. ### Claim 15 A memory system including a resistive memory device, the memory system comprising: a memory cell array; a write/read circuit; and control logic circuitry, wherein the control logic circuitry is configured to: determine whether to perform a refresh operation on memory cells in the memory cell array; determine a respective resistance state of each of the memory cells, when the refresh operation is determined to be performed; classify the memory cells within the memory cell array as first memory cells having resistance states that are determined to be equal to or less than a critical resistance level and second memory cells having resistance states that are determined to be greater than the critical resistance level; and instruct the write/read circuit to perform a re-writing operation on the first memory cells among the memory cells. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the re-writing operation comprises a set writing operation but not a reset writing operation. ### Claim 17 (depends on 15) The memory system of claim 15, wherein the re-writing operation comprises applying a current pulse to each of the first memory cells. ### Claim 18 (depends on 15) The memory system of claim 15, wherein each of the first memory cells has a resistance state other than an uppermost resistance state from among a plurality of resistance states. ### Claim 19 (depends on 15) The memory system of claim 15, wherein the control logic circuitry is configured to instruct the write/read circuit to perform a pre-reading operation on some of the memory cells.