# US 9,437,288 B2 · Dual mode clock and data scheme for memory programming

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- Number: US 9,437,288 B2
- Document ID: US9437288B2
- Status: Granted
- Kind: B2
- Application number: 14/456,896
- Filed: 2014-08-11
- Published: 2014-11-27
- Granted: 2016-09-06
- Earliest claimed: 2009-09-11
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kerry Dean Tedrow
- Web page: https://patentgrep.com/patent/US9437288B2

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/12015: {comprising clock generation or timing circuitry}
- G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual edge clock. A transition detector generated internal clock provides a delayed edge to latch the program data. This dual-edge clock scheme provides a doubling in the data transfer rate.

## Claims

### Claim 1

A memory device comprising a factory interface to receive factory program data on a data bus switching with a dual edge clock where a transition detector generated internal clock provides a delayed edge to latch the factory program data for storage in the memory device, wherein the factory interface and the transition detector are located in the memory device.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the transition detector includes a two-input semiconductor device to receive the dual edge clock and a delayed version of the dual edge clock to generate a pulsed signal.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the transition detector circuit detects a transition on the dual edge clock and generates the pulsed signal to latch the program data.

### Claim 4 (depends on 1)

The memory device of claim 1, further including a program buffer coupled to the factory interface to receive latched program data to prepare for storage in memory arrays in the memory device.

### Claim 5

A memory device, comprising:
a system memory interface to operate in a system mode selected as a default operating mode to receive data and commands from a data bus; and
a factory programming interface to operate in a factory programming mode to receive factory program data on the data bus and a dual edge clock that is used to generate an internal clock from a transition detector to provide a delayed edge to latch the factory program data, wherein the factory programming interface and the transition detector are located in the memory device.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the factory program data received from an external source switches with transitions of the dual edge clock.

### Claim 7 (depends on 5)

The memory device of claim 5, wherein a command received through the data bus instructs the memory device to switch to the factory programming mode.

### Claim 8 (depends on 5)

The memory device of claim 5, wherein a command received on the data bus instructs the memory device to revert back to the system mode.

### Claim 9 (depends on 5)

The memory device of claim 5, wherein an input pin directs the memory device to operate in the system mode or the factory programming mode.

### Claim 10 (depends on 5)

The memory device of claim 5, wherein a transition detector of the memory device generates the internal clock.

### Claim 11 (depends on 5)

The memory device of claim 5, wherein the factory programming interface uses the dual-edge clock scheme to provide a doubling in the data transfer rate.

### Claim 12 (depends on 5)

The memory device of claim 5, wherein the transition detector receives the dual edge clock to generate a pulsed signal.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the transition detector circuit detects a transition on the dual edge clock to generate the pulsed signal to latch the program data.

### Claim 14

A memory device comprising:
a memory array;
a system memory interface operating in a system mode for executing system applications; and
a factory programming interface operating in a factory programming mode to receive program data on a data bus and to generate an internal clock from a transition detector to provide a delayed edge to latch the program data, wherein the factory programming interface is located in the memory device.

### Claim 15 (depends on 10)

The memory device of claim 10, wherein the memory device operating in a factory programming mode redefines one or more control pins as data pins to increase a width of the data bus and increase a programming data rate.

### Claim 16 (depends on 10)

The memory device of claim 10 wherein the factory programming interface receives factory program data switching with transitions of a dual edge clock.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein the transition detector is included in the factory programming interface program data for storage in the device.

### Claim 18 (depends on 14)

The memory device of claim 14, wherein the factory programming interface uses a dual-edge clock scheme to provide a doubling in the data transfer rate.

### Claim 19 (depends on 14)

The memory device of claim 14, wherein the transition detector receives a dual edge clock and a delayed version of the dual edge clock to generate a pulsed signal.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein the transition detector circuit detects a transition on the dual edge clock to generate the pulsed signal to latch the program data.