# US 9,437,284 B1 · Memory devices and control methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,284 B1 - Document ID: US9437284B1 - Status: Granted - Kind: B1 - Application number: 14/957,311 - Filed: 2015-12-02 - Granted: 2016-09-06 - Earliest claimed: 2015-12-02 - Assignees: Vanguard International Semiconductor Corporation - Applicants: Vanguard International Semiconductor Corporation - Inventors: Jui-Lung Chen; Wei-Ting Chen; Yu-Hsi Ke - Web page: https://patentgrep.com/patent/US9437284B1 ## CPC - G11C 11/419: Read-write [R-W] circuits - G11C 11/412: using field-effect transistors only - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 11/418: Address circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device is provided. The memory device includes a memory device, a plurality of word lines and bit lines, first and second decoders, and a control circuit. The memory array includes memory cells on rows and columns. Each word line is coupled to the memory cells in one row. Each bit line is coupled to the memory cells in one column. The first decoder selects one word line according to an address signal and a first control signal. The control circuit respectively generates the first control signal and the second control signal according to a first clock signal and a second clock signal. In the period during which the first decoder selects the one word line, the second decoder selects at least two bit lines according to the address signal and a second control signal. The memory device performs a read/write operation on the selected bit lines. ## Claims ### Claim 1 A memory device comprising: a memory array comprising a plurality of memory cells disposed on a plurality of rows and a plurality of columns; a plurality of word lines, each coupled to the memory cells disposed on one of the plurality of rows; a plurality of bit lines, each coupled to the memory cells disposed on one of the plurality of columns; a first decoder receiving an address signal and a first control signal and selecting one of the plurality of word lines according to the address signal and the first control signal; a second decoder receiving the address signal and a second control signal; and a control circuit receiving a first clock signal and a second clock signal, generating the first control signal according to the first clock signal, and generating the second signal according to the second clock signal, wherein in a period during which the first decoder selects the one of the plurality of word lines according to the address signal and the first control signal, the second decoder selects at least two of the plurality of bit lines according to the address signal and the second control signal, and the memory device performs a read/write operation on the selected at least two of the plurality of bit lines. ### Claim 2 (depends on 1) The memory device as claimed in claim 1, wherein the first clock signal comprises a plurality of first pulses, the second clock signal comprises a plurality of second pulses, and in a during of each of the plurality of first pulses, at least two of the plurality of second pulses occur. ### Claim 3 (depends on 1) The memory device as claimed in claim 1, wherein whenever a positive-edge trigger event of the first clock signal occurs, decoder to select one of the plurality of word lines according to the address signal, wherein whenever a positive-edge trigger event of the second clock signal occurs, the control circuit generates the second control signal to enable the second decoder to select one of the plurality of bit lines according to the address signal, and wherein in a period between a first time point at which the positive-edge triggering event of the first clock signal occurs and a second time point at which the positive-edge triggering event of the first clock signal occurs again after the time point, the positive-edge triggering event of the second clock signal occurs several times. ### Claim 4 (depends on 1) The memory device as claimed in claim 1, wherein in the period during which the first decoder selects the one of the plurality of word lines according to the address signal and the first control signal, the memory device performs a pre-charging operation on the plurality of bit lines only one time. ### Claim 5 (depends on 1) The memory device as claimed in claim 1, wherein in the period during which the first decoder selects the one of the plurality of word lines according to the address signal and the first control signal, the memory device performs a read/write operation on at least two of the plurality of bit lines to read or write serial data. ### Claim 6 (depends on 5) The memory device as claimed in claim 5, wherein the memory device reads or writes the serial data in a frame-page mode, a packet mode, or a sequence mode. ### Claim 7 (depends on 1) The memory device as claimed in claim 1, wherein the memory device is a static random access memory (SRAM). ### Claim 8 (depends on 1) The memory device as claimed in claim 1, wherein the memory device is a buffer device. ### Claim 9 A control method for a memory device which comprises a memory array, a plurality of word lines coupled to the memory device, and a plurality of bit lines coupled to the memory device, the control method comprising: receiving a first clock signal and a second clock signal; generating a first control signal according to the first clock signal; generating a second signal according to the second clock signal; selecting one of the plurality of word lines according to an address signal and an enable state of the first control signal; in a period during which the one of the plurality of word lines according to the address signal and the first control signal is selected, selecting at least two of the plurality of bit lines according to the address signal and an enable signal of the second control signal; and performing a read/write operation on the selected at least two of the plurality of bit lines. ### Claim 10 (depends on 9) The control method as claimed in claim 9, wherein the first clock signal comprises a plurality of first pulses, the second clock signal comprises a plurality of second pulses, and in a during of each of the plurality of first pulses, at least two of the plurality of second pulses occur. ### Claim 11 (depends on 9) The control method as claimed in claim 9, wherein whenever a positive-edge trigger event of the first clock signal occurs, the first control signal is enabled, wherein whenever a positive-edge trigger event of the second clock signal occurs, the second control signal is enabled, and wherein in a period between a first time point at which the positive-edge triggering event of the first clock signal occurs and a second time point at which the positive-edge triggering event of the first clock signal occurs again after the time point, the positive-edge triggering event of the second clock signal occurs several times. ### Claim 12 (depends on 9) The control method as claimed in claim 9, further comprising: in the period during which the one of the plurality of word lines according to the address signal and the first control signal, performing a pre-charging operation on the plurality of bit lines only one time. ### Claim 13 (depends on 9) The control method as claimed in claim 9, wherein the step of performing the read/write operation comprises: reading or writing serial data. ### Claim 14 (depends on 13) The control method as claimed in claim 13, wherein the serial data is read or written in a frame-page mode, a packet mode, or a sequence mode.