# US 9,437,280 B2 · DRAM sense amplifier that supports low memory-cell capacitance

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- Number: US 9,437,280 B2
- Document ID: US9437280B2
- Status: Granted
- Kind: B2
- Application number: 14/506,507
- Filed: 2014-10-03
- Published: 2015-04-16
- Granted: 2016-09-06
- Earliest claimed: 2009-12-04
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Thomas Vogelsang; Gary B. Bronner
- Web page: https://patentgrep.com/patent/US9437280B2

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/08: Control thereof
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- H10B 12/50: {Peripheral circuit region structures}
- H10B 12/05: {Making the transistor}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line.

## Claims

### Claim 1

A dynamic random access memory (“DRAM”) integrated circuit, comprising:
memory cells; and
sense amplifiers to sense respective ones of the memory cells;
wherein each of the sense amplifiers has
a bistable circuit, the bistable circuit having a pair of transistors having matched threshold voltages, each transistor in the pair characterized by a gate material having a work function of between 4.5 to 4.7 volts, and threshold voltage of less than 0.5 volts, the bistable circuit to sense voltage retained by the respective memory cell, and
a latch circuit to latch an output produced by the transistor bistable circuit.

### Claim 2 (depends on 1)

The DRAM integrated circuit of claim 1, wherein:
each of the transistors is a n-type field effect transistor (NFET) and is characterized by a dopant concentration of less than 1017 atoms per cubic centimeter.

### Claim 3 (depends on 2)

The DRAM integrated circuit of claim 2, wherein:
each of the NFETs has a metal gate.

### Claim 4 (depends on 3)

The DRAM integrated circuit of claim 3, wherein:
each of the metal gates has a metallic compound selected from the group of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), aluminum nitride (AlN), Iridium (Ir), Iridium Oxide (IrO) and nickel (Ni).

### Claim 5 (depends on 1)

The DRAM integrated circuit of claim 1, wherein:
each of the transistors has a threshold voltage of less than 0.3 volts.

### Claim 6

A dynamic random access memory (“DRAM”) integrated circuit, comprising:
memory cells; and
sense amplifiers to sense respective ones of the memory cells;
wherein each of the sense amplifiers has a bistable circuit that includes matched transistors, including a first transistor and a second transistor, to sense voltage retained by the respective memory cell, each of said matched transistors characterized by a gate material having a work function of between 4.5 to 4.7 volts a threshold voltage of less than 0.5 volts, and a latch circuit to receive an output of the bistable circuit and to latch the output.

### Claim 7 (depends on 6)

The DRAM integrated circuit of claim 6, wherein:
each of the first transistor and the second transistor is a n-type field effect transistor (NFET) and is characterized by a dopant concentration of less than 1017 atoms per cubic centimeter.

### Claim 8 (depends on 6)

The DRAM integrated circuit of claim 6, wherein:
each of the first transistor and the second transistor is coupled in series with a control transistor to ground, the control transistors actuated to cause the first transistor and the second transistor to sense state of the respective memory cell.

### Claim 9 (depends on 6)

The DRAM integrated circuit of claim 6, wherein:
each of first transistor and the second transistor has a metal gate with a metallic compound selected from the group of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), aluminum nitride (AlN), Iridium (Ir), Iridium Oxide (IrO) and nickel (Ni).

### Claim 10 (depends on 6)

The DRAM integrated circuit of claim 6, wherein:
each of the first transistor and the second transistor has a threshold voltage of less than 0.3 volts.

### Claim 11

A dynamic random access memory (“DRAM”) integrated circuit, comprising:
memory cells; and
sense amplifiers to sense respective ones of the memory cells;
wherein each of the sense amplifiers has a pair of matched transistors to sense voltage retained by the respective memory cell, each of the matched transistors having a threshold voltage of less than 0.5 volts and a metal gate characterized by a work function of between 4.5 to 4.7 volts.

### Claim 12 (depends on 11)

The DRAM integrated circuit of claim 11, wherein:
each of the matched transistors is coupled in series with a control transistor to ground to sense state of the respective memory cell.

### Claim 13 (depends on 11)

The DRAM integrated circuit of claim 11, wherein:
each of the matched transistors is a n-type field effect transistor (NFET) and is characterized by a dopant concentration of less than 1017 atoms per cubic centimeter.

### Claim 14 (depends on 11)

The DRAM integrated circuit of claim 11, wherein:
the metal gate has a metallic compound selected from the group of tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), aluminum nitride (AlN), Iridium (Ir), Iridium Oxide (IrO) and nickel (Ni).

### Claim 15 (depends on 1)

The DRAM integrated circuit of claim 1, wherein for each of the sense amplifiers, a first transistor in the pair is to couple a bit line to ground upon being actuated, and a second transistor in the pair is to couple a complement bit line to ground upon being actuated.

### Claim 16 (depends on 15)

The DRAM integrated circuit of claim 15, wherein each of the sense amplifiers further comprises a first p-type field effect transistor (PFET) to couple the bit line for the corresponding memory cell to a non-zero voltage upon being actuated, and second PFET to couple a complement bit line to the non-zero voltage upon being actuated.

### Claim 17 (depends on 1)

The DRAM integrated circuit of claim 1, wherein for each of the second amplifiers the pair of transistors is a first pair of transistors, and wherein each of the sense amplifiers further comprises a second pair of transistors, the first pair of transistors to initially sense voltage on a bit line in the corresponding memory cell, the second pair of transistors to latch voltage on the bit line in the corresponding memory cell following initial sense of the bit line by the first memory cell.

### Claim 18 (depends on 6)

The DRAM integrated circuit of claim 6, wherein for each of the sense amplifiers, the first transistor is to couple a bit line to ground upon being actuated, and the second transistor is to couple a complement bit line to ground upon being actuated.

### Claim 19 (depends on 18)

The DRAM integrated circuit of claim 18, wherein each of the sense amplifiers further comprises a first p-type field effect transistor (PFET) to couple the bit line for the respective memory cell to a non-zero voltage upon being actuated, and second PFET to couple a complement bit line to the non-zero voltage upon being actuated.

### Claim 20 (depends on 6)

The DRAM integrated circuit of claim 6, wherein for each of the second amplifiers the matched transistors is a first pair of transistors, and wherein each of the sense amplifiers further comprises a second pair of transistors, the first pair of transistors to initially sense voltage on a bit line in the corresponding memory cell, the second pair of transistors to latch voltage on the bit line in the corresponding memory cell following initial sense of the bit line by the first memory cell.