# US 9,437,276 B2 · Maintenance operations in a DRAM

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- Number: US 9,437,276 B2
- Document ID: US9437276B2
- Status: Granted
- Kind: B2
- Application number: 15/132,017
- Filed: 2016-04-18
- Published: 2016-08-11
- Granted: 2016-09-06
- Earliest claimed: 2009-01-22
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Frederick A. Ware; Robert E. Palmer; John W. Poulton
- Web page: https://patentgrep.com/patent/US9437276B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 13/1636: {using refresh}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06Q 10/00: Administration; Management
- G06Q 20/00: Payment architectures, schemes or protocols (apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12)
- G11C 7/02: with means for avoiding parasitic signals
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 29/025: {in signal lines}
- G11C 2211/4061: Calibration or ate or cycle tuning
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06Q: INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR

## Abstract

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

## Claims

### Claim 1

A method of operating a memory controller that controls the operation of a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:
the memory controller transmitting a refresh command, along with a plurality of bits, to the command interface of the memory device, wherein responsive to the refresh command, during a first time interval, the memory device performs a refresh operation to refresh data stored in at least one bank of the plurality of memory banks, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence; and
transmitting an operation code from the memory controller to the memory device, the operation code specifying a calibration operation of the command interface;
wherein, after receiving the operation code, the memory device is to perform the calibration operation of the command interface of the memory device while performing the refresh operation to the at least one bank identified by the plurality of bits.

### Claim 2 (depends on 1)

The method of claim 1, including configuring the command interface of the memory device to perform the calibration operation, in accordance with the operation code transmitted by the memory controller to the memory device.

### Claim 3 (depends on 1)

The method of claim 1, wherein performing the calibration operation includes placing the command interface of the memory device into a loopback mode.

### Claim 4 (depends on 1)

The method of claim 1, wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

### Claim 5 (depends on 1)

The method of claim 1 wherein the plurality of bits includes a plurality of fields indicating the order in which the plurality of banks are to be refreshed in the sequence, the plurality of fields including a first field to specify the first bank in the sequence and a second field to specify a second bank in the sequence.

### Claim 6 (depends on 1)

The method of claim 1, further comprising, while performing the calibration operation of the command interface, concurrently transmitting to the memory device, information from the memory controller on a first data path and receiving data from the memory device on a second data path.

### Claim 7 (depends on 6)

The method of claim 6, wherein performing the calibration operation of the command interface of the memory device includes performing a timing calibration.

### Claim 8 (depends on 7)

The method of claim 7, wherein performing the timing calibration comprises:
transmitting from the memory controller a pattern to the command interface of the memory device on the first data path;
receiving at the memory controller the pattern from the command interface of the memory device on the second data path;
comparing the received signal and the transmitted pattern; and
performing phase compensation based on the comparison.

### Claim 9 (depends on 8)

The method of claim 8, wherein said transmitting, receiving and comparing are repeated a plurality of times, using a plurality of different timing offsets, said performing phase compensation including identifying first and second timing offsets associated with opposing edges of a data eye to generate a calibrated timing offset between the first and second timing offsets.

### Claim 10 (depends on 1)

The method of claim 1, wherein performing the calibration operation of the command interface of the memory device includes performing an offset voltage calibration including:
determining a value representing a receiver voltage offset for a sampler of the memory device; and
storing the value in the memory device.

### Claim 11

A memory controller that controls the operation of a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
a circuit to output a refresh command, along with a plurality of bits, to the command interface of the memory device, wherein responsive to the refresh command, during a first time interval, the memory device performs a refresh operation to refresh data stored in at least one bank of the plurality of memory banks, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence; and
a circuit to generate an operation code specifying a calibration operation of the command interface of the memory device;
wherein, after receiving the operation code, the memory device is to perform the calibration operation of the command interface of the memory device while performing the refresh operation to the at least one bank identified by the plurality of bits.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein the circuit to output the refresh command is a circuit to transmit the operation code with the refresh command to the memory device, the operation code being transmitted with the refresh command to instruct the memory device to perform the calibration operation.

### Claim 13 (depends on 12)

The memory controller of claim 12, wherein the calibration operation includes placing the command interface of the memory device into a loopback mode.

### Claim 14 (depends on 11)

The memory controller of claim 11, wherein the refresh operation is specified as an auto-refresh operation, wherein a row of memory cells is refreshed in the at least one bank identified by the plurality of bits.

### Claim 15 (depends on 11)

The memory controller of claim 11, wherein the plurality of bits includes a plurality of fields indicating the order in which the plurality of banks are to be refreshed in the sequence, the plurality of fields including a first field to specify the first bank in the sequence and a second field to specify a second bank in the sequence.

### Claim 16 (depends on 11)

The memory controller of claim 11, further comprising, a circuit to transmit information from the memory controller on a first data path and receive data from the memory device on a second data path during the calibration operation.

### Claim 17 (depends on 11)

The memory controller of claim 11, further comprising a circuit to perform timing calibration operation of the command interface of the memory device.

### Claim 18 (depends on 11)

The memory controller of claim 11, wherein the circuit to generate the refresh command is a command sequencer.

### Claim 19 (depends on 11)

The memory controller of claim 11, further comprising:
a circuit to generate a pattern to transmitted to the command interface of the memory device on a first data path;
a circuit to receive the pattern from the command interface of the memory device via a second data path;
a circuit to compare the received signal and the transmitted pattern; and
a circuit apply a phase compensation based on the comparison.

### Claim 20

A memory controller that controls the operation of a memory device, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
means for outputting a refresh command, along with a plurality of bits, to the command interface of the memory device, wherein responsive to the refresh command, during a first time interval, the memory device performs a refresh operation to refresh data stored in at least one bank of the plurality of memory banks, the plurality of bits to identify at least one bank as a first bank of the plurality of banks to be refreshed in a sequence; and
means for generating an operation code specifying a calibration operation of the command interface of the memory device;
wherein, after receiving the operation code, the memory device is to perform the calibration operation of the command interface of the memory device while performing the refresh operation to the at least one bank identified by the plurality of bits.