# US 9,437,273 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,273 B2 - Document ID: US9437273B2 - Status: Granted - Kind: B2 - Application number: 14/139,248 - Filed: 2013-12-23 - Published: 2014-06-26 - Granted: 2016-09-06 - Earliest claimed: 2012-12-26 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shunpei Yamazaki; Jun Koyama - Web page: https://patentgrep.com/patent/US9437273B2 ## CPC - G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 11/5621: {using charge storage in a floating gate} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract To provide a semiconductor device that has a novel structure and achieves a higher degree of convenience, the semiconductor device is configured to include a memory cell that stores binary data or multilevel data, and a reading circuit that reads the data stored in the memory cell and transfers the data to the outside. The reading circuit includes a first reading circuit for reading binary data and a second reading circuit for reading multilevel data. ## Claims ### Claim 1 A semiconductor device comprising: a switch; a bit line electrically connected to a first terminal of the switch; a word line; a memory cell electrically connected to the bit line and the word line; a first comparator electrically connected to a second terminal of the switch; a second comparator electrically connected to a third terminal of the switch; and a third comparator electrically connected to the third terminal of the switch, wherein the memory cell is configured to store binary data or multilevel data, wherein the binary data is supplied from the bit line to the first comparator through the switch when the binary data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the second comparator through the switch when the multilevel data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the third comparator through the switch when the multilevel data is read from the memory cell, wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell, wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, and wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the memory cell comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to the bit line, and wherein the first transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell. ### Claim 5 (depends on 3) The semiconductor device according to claim 3, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is supplied to the first comparator, the second comparator, and the third comparator when the multilevel data is read from the memory cell. ### Claim 6 A semiconductor device comprising: a switch; a bit line electrically connected to a first terminal of the switch; a word line; a memory cell electrically connected to the bit line and the word line; a first comparator electrically connected to a second terminal of the switch; a second comparator electrically connected to a third terminal of the switch; a third comparator electrically connected to the third terminal of the switch; and a writing circuit electrically connected to the bit line, wherein the memory cell is configured to store binary data or multilevel data, wherein the binary data is supplied from the bit line to the first comparator through the switch when the binary data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the second comparator through the switch when the multilevel data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the third comparator through the switch when the multilevel data is read from the memory cell, wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell, wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell, wherein the writing circuit is configured to output one of a first voltage and a second voltage to the memory cell through the bit line in accordance with the binary data, and wherein the writing circuit is configured to output one of a third voltage, a fourth voltage, and a fifth voltage to the memory cell through the bit line in accordance with the multilevel data. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the memory cell comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to the bit line, and wherein the first transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein a power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is supplied to the first comparator, the second comparator, and the third comparator when the multilevel data is read from the memory cell. ### Claim 11 A semiconductor device comprising: a bit line; a word line; a memory cell electrically connected to the bit line and the word line; a first switch electrically connected to the bit line; a second switch; a first comparator electrically connected to a first terminal of the first switch and a first terminal of the second switch; a second comparator electrically connected to a second terminal of the first switch and a second terminal of the second switch; a third comparator electrically connected to the second terminal of the first switch and the second terminal of the second switch; a writing circuit electrically connected to the bit line; and a voltage generator circuit electrically connected to the second switch. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the memory cell is configured to store binary data or multilevel data, wherein the binary data is supplied from the bit line to the first comparator through the first switch when the binary data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the second comparator through the first switch when the multilevel data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the third comparator through the first switch when the multilevel data is read from the memory cell, wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell, wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell, wherein the writing circuit is configured to output one of a first voltage and a second voltage to the memory cell through the bit line in accordance with the binary data, wherein the writing circuit is configured to output one of a third voltage, a fourth voltage, and a fifth voltage to the memory cell through the bit line in accordance with the multilevel data, and wherein the voltage generator circuit is configured to supply a power supply voltage to the first comparator, the second comparator, and the third comparator through the second switch. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the power supply voltage is supplied to the first comparator and is not supplied to the second comparator and the third comparator when the binary data is read from the memory cell, and wherein the power supply voltage is not supplied to the first comparator and is supplied to the second comparator and the third comparator when the multilevel data is read from the memory cell. ### Claim 14 (depends on 11) The semiconductor device according to claim 11, wherein the memory cell comprises a first transistor and a second transistor, wherein a first terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to the bit line, and wherein the first transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the memory cell is configured to store binary data or multilevel data, wherein the binary data is supplied from the bit line to the first comparator through the first switch when the binary data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the second comparator through the first switch when the multilevel data is read from the memory cell, wherein the multilevel data is supplied from the bit line to the third comparator through the first switch when the multilevel data is read from the memory cell, wherein the first comparator is configured to compare a level of a first reference voltage and a voltage corresponding to the binary data read from the memory cell, wherein the second comparator is configured to compare a level of a second reference voltage and a voltage corresponding to the multilevel data read from the memory cell, wherein the third comparator is configured to compare a level of a third reference voltage and the voltage corresponding to the multilevel data read from the memory cell, wherein the writing circuit is configured to output one of a first voltage and a second voltage to the memory cell through the bit line in accordance with the binary data, wherein the writing circuit is configured to output one of a third voltage, a fourth voltage, and a fifth voltage to the memory cell through the bit line in accordance with the multilevel data, and wherein the voltage generator circuit is configured to supply a power supply voltage to the first comparator, the second comparator, and the third comparator through the second switch. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the power supply voltage is supplied from the voltage generator circuit to the first comparator through the second switch when the binary data is read from the memory cell, wherein the power supply voltage is not supplied from the voltage generator circuit to the second comparator and the third comparator through the second switch when the binary data is read from the memory cell, wherein the power supply voltage is not supplied from the voltage generator circuit to the first comparator through the second switch when the multilevel data is read from the memory cell, and wherein the power supply voltage is supplied from the voltage generator circuit to the second comparator and the third comparator through the second switch when the multilevel data is read from the memory cell.