# US 9,437,272 B1 · Multi-bit spin torque transfer magnetoresistive random access memory with sub-arrays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,272 B1 - Document ID: US9437272B1 - Status: Granted - Kind: B1 - Application number: 14/645,213 - Filed: 2015-03-11 - Published: 2016-09-15 - Granted: 2016-09-06 - Earliest claimed: 2015-03-11 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Yu Lu; Xia Li - Web page: https://patentgrep.com/patent/US9437272B1 ## CPC - G11C 11/1673: {Reading or sensing circuits or methods} - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1659: {Cell access} - G11C 11/5607: {using magnetic storage elements} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also includes an access transistor coupled between the first MTJ element and the second MTJ element. A gate of the access transistor is coupled to a word line. The first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell. ## Claims ### Claim 1 A device comprising: a first magnetic tunnel junction (MTJ) element having a first read margin; a second MTJ element having a second read margin, the first read margin greater than twice the second read margin; an access transistor coupled between the first MTJ element and the second MTJ element, wherein a gate of the access transistor is coupled to a word line, and wherein the first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell; and circuitry configured to compare a sensed value of the STT-MRAM memory cell to a second value, the second value based on a comparison of the sensed value to a first value. ### Claim 2 (depends on 1) The device of claim 1, further comprising a bit line coupled to the first MTJ element and a source line coupled to the second MTJ element, wherein the circuitry is further configured to determine a resistive state of the second MTJ element based on a relation of the sensed value to the second value. ### Claim 3 (depends on 1) The device of claim 1, wherein the access transistor is configured to couple the first MTJ element to the second MTJ element responsive to a word line signal. ### Claim 4 (depends on 1) The device of claim 1, wherein the access transistor is an n-type metal-oxide-semiconductor (NMOS) transistor. ### Claim 5 (depends on 1) The device of claim 1, wherein the access transistor is a p-type metal-oxide-semiconductor (PMOS) transistor. ### Claim 6 (depends on 1) The device of claim 1, wherein the first MTJ element has a first data retention time and the second MTJ element has a second data retention time that is longer than the first data retention time. ### Claim 7 (depends on 1) The device of claim 1, wherein the first MTJ element has a first size and the second MTJ element has a second size that is greater than twice the first size. ### Claim 8 (depends on 1) The device of claim 1, wherein the second MTJ element is associated with a first reference levels indicated by the first value and a second reference level indicated by the second value, and wherein the first MTJ element is associated with one reference level. ### Claim 9 (depends on 1) The device of claim 1, further comprising an apparatus selected from a mobile phone, a tablet, a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the first MTJ element, the second MTJ element, and the access transistor are integrated. ### Claim 10 A method of operation of a device that includes an access transistor, a first magnetic tunnel junction (MTJ) element, and a second MTJ element, the method comprising: activating the access transistor, wherein the first MTJ element and the second MTJ element are responsive to the access transistor, wherein the first MTJ element has a first size, and wherein the second MTJ element has a second size that is greater than twice the first size; and determining a resistive state of the second MTJ element by: performing a first comparison of a sensed value to a first reference value; and performing a second comparison of the sensed value to a second reference value, wherein the second reference value is based on a result of the first comparison. ### Claim 11 (depends on 10) The method of claim 10, further comprising applying a particular current at a bit line coupled to the first MTJ element, wherein the access transistor is activated via a word line signal applied to a gate of the access transistor, and wherein applying the particular current occurs prior to the determining of the resistive state. ### Claim 12 (depends on 10) The method of claim 10, wherein the first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell. ### Claim 13 (depends on 12) The method of claim 12, wherein a resistive state of the first MTJ element and the resistive state of the second MTJ element are based on one or more combinations of a parallel state or anti-parallel state of the first MTJ element with a parallel state or anti-parallel state of the second MTJ element. ### Claim 14 An apparatus comprising: first means for storing a first magnetic state, wherein the first means for storing has a first size; second means for storing a second magnetic state, wherein the second means for storing has a second size that is greater than twice the first size; means for coupling the first means for storing and the second means for storing, wherein the means for coupling is coupled to a word line, and wherein the first means for storing, the second means for storing, and the means for coupling form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell; and means for comparing a sensed value of the STT-MRAM memory cell to a second value, the second value based on a comparison of the sensed value to a first value. ### Claim 15 (depends on 14) The apparatus of claim 14, further comprising a bit line coupled to the first means for storing and a source line coupled to the second means for storing, the means for coupling configured to couple the first means for storing to the second means for storing in response to a word line signal, the first value indicating a first reference level associated with the second means for storing, the second value indicating a second reference level associated with the second means for storing, and the means for comparing further configured to determine a resistive state of the second means for storing based on a relation of the sensed value to the second value. ### Claim 16 An apparatus comprising: a first magnetic tunnel junction (MTJ) sub-array formed by a plurality of first MTJ elements of a memory array; a second MTJ sub-array formed by a plurality of second MTJ elements of the memory array, wherein the first MTJ sub-array is configured to operate based on a first set of parameters for a first memory use and the second MTJ sub-array is configured to operate based on a second set of parameters for a second memory use that is different from the first memory use; and circuitry configured to compare a sensed value associated with an MTJ element of the plurality of second MTJ elements to a second value, the second value based on a comparison of the sensed value to a first value. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the circuitry is further configured to determine a resistive state of the MTJ element based on a relation of the sensed value to the second value, wherein each MTJ element of the plurality of first MTJ elements has a first size, and wherein each MTJ element of the plurality of second MTJ elements has a second size that is greater than twice the first size. ### Claim 18 (depends on 16) The apparatus of claim 16, further comprising a memory controller configured to address each of the plurality of first MTJ elements of the first MTJ sub-array and each of the plurality of second MTJ elements of the second MTJ sub-array. ### Claim 19 (depends on 16) The apparatus of claim 16, further comprising a memory controller configured to store data at the first MTJ sub-array or at the second MTJ sub-array based on a priority indicator received at the memory controller from a central processing unit (CPU), the priority indicator indicating a priority level associated with the data to be stored. ### Claim 20 A non-transitory computer-readable medium storing instructions, which when executed by a processor of an apparatus, cause the processor to perform operations comprising: activating an aces transistor, wherein a first MTJ element and a second MTJ element at the apparatus are responsive to the access transistor, wherein the first MTJ element has a first size, and wherein the second MTJ element has a second size that is greater than twice the first size; and determining a resistive state of the second MTJ element by: performing a first comparison of a sensed value to a first reference value; and performing a second comparison of the sensed value to a second reference value, wherein the second reference value is based on a result of the first comparison. ### Claim 21 (depends on 20) The non-transitory computer-readable medium of claim 20, wherein the operations further comprise storing data at the first MTJ element or at the second MTJ element based on a priority indicator that indicates a priority level associated with the data to be stored. ### Claim 22 (depends on 16) The apparatus of claim 16, wherein the second MTJ sub-array is configured to store data values that are duplicate values of corresponding data that is stored at the first MTJ sub-array. ### Claim 23 (depends on 16) The apparatus of claim 16, wherein the first MTJ sub-array is configured to operate as a data cache. ### Claim 24 (depends on 16) The apparatus of claim 16, wherein the second MTJ sub-array is configured to operate as a temporary storage array for the first MTJ sub-array. ### Claim 25 (depends on 16) The apparatus of claim 16, wherein the second MTJ sub-array is configured to store data that is used as part of a sleep-mode operation of an electronic device. ### Claim 26 (depends on 16) The apparatus of claim 16, wherein the second MTJ sub-array is configured to store data that is used as part of an initialization operation of an electronic device. ### Claim 27 (depends on 16) The apparatus of claim 16, wherein the first set of parameters is based on physical characteristics of each of the plurality of first MTJ elements, and wherein the second set of parameters is based on physical characteristics of each of the plurality of second MTJ elements. ### Claim 28 (depends on 27) The apparatus of claim 27, wherein the physical characteristics of the first MTJ elements include a first size, and wherein the physical characteristics of the second MTJ elements include a second size that is greater than twice the first size. ### Claim 29 (depends on 16) The apparatus of claim 16, wherein the first MTJ sub-array and the second MTJ sub-array are integrated in at least one die. ### Claim 30 (depends on 16) The apparatus of claim 16, further comprising a device selected from a mobile phone, a tablet, a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the first MTJ sub-array and the second MTJ sub-array are integrated.