# US 9,437,271 B2 · Electronic devices having semiconductor magnetic memory units > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,271 B2 - Document ID: US9437271B2 - Status: Granted - Kind: B2 - Application number: 14/058,079 - Filed: 2013-10-18 - Published: 2014-08-28 - Granted: 2016-09-06 - Earliest claimed: 2013-02-28 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Ji-Wang Lee - Web page: https://patentgrep.com/patent/US9437271B2 ## CPC - G11C 13/004: {Reading or sensing circuits or methods} - G06F 3/061: {Improving I/O performance} - G06F 3/0656: {Data buffering arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 11/1659: {Cell access} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1697: {Power supply circuits} - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G06F 2212/2024: Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM - G06F 2212/60: Details of cache memory - G11C 2013/0045: {Read using current through the cell} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2213/79: Array wherein the access device being a transistor - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An electronic device comprising a semiconductor memory unit that includes a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input terminal. ## Claims ### Claim 1 An electronic device comprising a semiconductor memory unit that includes: a resistance variable element configured to exhibit a first resistance value for storing first data and a second resistance value larger than the first resistance value for storing second data different from the first data; a first reference resistance element having a first reference resistance value and electrically coupled to be separate from the resistance variable element without having a current to flow through both the first reference resistance element and the resistance variable element in operating the semiconductor memory unit; a second reference resistance element having a second reference resistance value and electrically coupled to be separate from the resistance variable element without having a current to flow through both the second reference resistance element and the resistance variable element in operating the semiconductor memory unit; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first reference resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second reference resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing a sum of the voltage inputted to the first input terminal and the voltage inputted to the second input terminal and a sum of the voltage inputted to the third input terminal and the voltage inputted to the fourth input terminal and to determine whether a resistance value of the resistance variable element represents the first data or the second data. ### Claim 2 (depends on 1) The electronic device according to claim 1, further comprising: a first current source configured to supply a read current to the resistance variable element; a second current source configured to supply the read current to the first reference resistance element; and a third current source configured to supply the read current to the second reference resistance element. ### Claim 3 (depends on 2) The electronic device according to claim 2, wherein one end of the resistance variable element is connected to the first input terminal and the second input terminal, one end of the first reference resistance element is connected to the third input terminal, one end of the second reference resistance element is connected to the fourth input terminal, and a power supply voltage is applied to the other ends of the resistance variable element, the first reference resistance element and the second reference resistance element. ### Claim 4 (depends on 2) The electronic device according to claim 2, wherein one end of the resistance variable element is connected to the first input terminal and the second input terminal, one end of the first reference resistance element is connected to the third input terminal, one end of the second reference resistance element is connected to the fourth input terminal, and a ground voltage is applied to the other ends of the resistance variable element, the first reference resistance element and the second reference resistance element. ### Claim 5 (depends on 1) The electronic device according to claim 1, wherein the comparison unit comprises: a first current sourcing unit configured to source a current of a first node; a second current sourcing unit configured to source a current of a second node; a first current sinking unit configured to sink a current from the first node in response to the voltage inputted to the first input terminal and the voltage inputted to the second input terminal; and a second current sinking unit configured to sink a current from the second node in response to the voltage inputted to the third input terminal and the voltage inputted to the fourth input terminal. ### Claim 6 (depends on 1) The electronic device according to claim 1, wherein the resistance variable element comprises a metal oxide, a phase change substance or a structure in which a tunnel barrier layer is interposed between two ferromagnetic layers. ### Claim 7 (depends on 1) The electronic device according to claim 1, further comprising a microprocessor which includes: a control unit that is configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of microprocessor; and an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor. ### Claim 8 (depends on 1) The electronic device according to claim 1, further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor. ### Claim 9 (depends on 1) The electronic device according to claim 1, further comprising a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between the processor, the auxiliary memory device or the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system. ### Claim 10 (depends on 1) The electronic device according to claim 1, further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system. ### Claim 11 (depends on 1) The electronic device according to claim 1, further comprising a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system. ### Claim 12 An electronic device comprising a semiconductor memory unit that includes: a resistance variable element configured to exhibit a first resistance value for storing first data and a second resistance value larger than the first resistance value for storing second data different from the first data; a first reference resistance element having a first reference resistance value; a second reference resistance element having a second reference resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first reference resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second reference resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing a sum of the voltage inputted to the first input terminal and the voltage inputted to the second input terminal and a sum of the voltage inputted to the third input terminal and the voltage inputted to the fourth input terminal and to determine whether a resistance value of the resistance variable element represents the first data or the second data, wherein the comparison unit is controlled in an amount of a current flowing therein, according to the voltages inputted to the first input terminal, the second input terminal, the third input terminal and the fourth input terminal, and outputs a result of comparing a sum of an amount of a current flowing in response to the voltage inputted to the first input terminal and an amount of a current flowing in response to the voltage inputted to the second input terminal with a sum of an amount of a current flowing in response to the voltage inputted to the third input terminal and an amount of a current flowing in response to the voltage inputted to the fourth input terminal. ### Claim 13 An electronic device comprising a semiconductor memory unit that includes: a resistance variable element configured to be changed in a resistance value according to a value of data stored therein; a first reference resistance element having a first resistance value; a second reference resistance element having a second resistance value larger than the first resistance value; and a comparison unit configured to receive a voltage corresponding to the resistance value of the resistance variable element through a first input terminal and a second input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a third input terminal, and a voltage corresponding to the second resistance value of the second reference resistance element through a fourth input terminal, the comparison unit configured to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and fourth input terminal, wherein the semiconductor memory unit further includes: in addition to the resistance variable element, a plurality of additional resistance variable elements each configured to be changed in a resistance value according to the value of the data stored therein; in addition to the first reference resistance element, one or more additional first reference resistance elements each having a respective first resistance value; and in addition to the second reference resistance element, one or more additional second reference resistance elements each having a respective second resistance value larger than the respective first resistance value; wherein the electronic device further includes a current source which is configured to supply a read current to a resistance variable element selected among the plurality of resistance variable elements, a first reference resistance element corresponding to the selected resistance variable element among the first reference resistance elements and a second reference resistance element corresponding to the selected resistance variable element among the second reference resistance elements; and wherein the comparison unit is configured to receive a voltage of one end of the selected resistance variable element through a first input terminal and a second input terminal thereof, a voltage of one end of the first reference resistance element corresponding to the selected resistance variable element through the third input terminal thereof, and a voltage of one end of the second reference resistance element corresponding to the selected resistance variable element through the fourth input terminal thereof, and the comparison unit is operable to output a result of comparing inputs to the first input terminal and the second input terminal and inputs to the third input terminal and the fourth input terminal. ### Claim 14 (depends on 13) The electronic device according to claim 13, wherein each resistance variable element comprises a metal oxide, a phase change substance or a structure in which a tunnel barrier layer is interposed between two ferromagnetic layers. ### Claim 15 (depends on 13) The electronic device according to claim 13, further comprising a microprocessor which includes: a control unit that is configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of microprocessor; and an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor. ### Claim 16 (depends on 13) The electronic device according to claim 13, further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor. ### Claim 17 (depends on 13) The electronic device according to claim 13, further comprising a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between the processor, the auxiliary memory device or the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system. ### Claim 18 (depends on 13) The electronic device according to claim 13, further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system. ### Claim 19 (depends on 13) The electronic device according to claim 13, further comprising a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system. ### Claim 20 An electronic device comprising a semiconductor memory unit that includes: a resistance variable element configured to exhibit a first resistance value for storing first data and a second resistance value larger than the first resistance value for storing the second data different from the first data; a first reference resistance element having a first reference resistance value; a second reference resistance element having a second reference resistance value; and a comparison unit coupled to the resistance variable element, the first reference resistance element and the second reference resistance element in three separate circuitry paths that are independent from one another to receive a voltage corresponding to the resistance value of the resistance variable element through an input terminal thereof, a voltage corresponding to the first resistance value of the first reference resistance element through a first input bar terminal thereof, and a voltage corresponding to the second resistance value of the second reference resistance element through a second input bar terminal thereof, and wherein the comparison unit is configured to output a result of comparing the voltage inputted to the input terminal with a voltage having a voltage level between the voltage inputted to the first input bar terminal and the voltage inputted to the second input bar terminal and to determine whether a resistance value of the resistance variable element represents the first data or the second data. ### Claim 21 (depends on 20) The electronic device according to claim 20, wherein the comparison unit is controlled in an amount of a current flowing therein, according to the voltages inputted to the input terminal, the first input bar terminal and the second input bar terminal, and outputs a result of comparing an amount of a current flowing in response to the voltage inputted to the input terminal with a sum of an amount of a current flowing in response to the voltage inputted to the first input bar terminal and an amount of a current flowing in response to the voltage inputted to the second input bar terminal. ### Claim 22 (depends on 20) The electronic device according to claim 20, wherein the resistance variable element includes a magnetic tunnel junction (MTJ) element in which a tunneling barrier layer is interposed between two ferromagnetic layers. ### Claim 23 (depends on 20) The electronic device according to claim 20, wherein the comparison unit comprises: a first current sourcing unit configured to source a current of a first node; a second current sourcing unit configured to source a current of a second node; a first current sinking unit configured to sink a current from the first node in response to the voltage inputted to the input terminal; and a second current sinking unit configured to sink a current from the second node in response to the voltage inputted to the first input bar terminal and the voltage inputted to the second input bar terminal.