# US 9,437,266 B2 · Unipolar programmable metallization cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,266 B2 - Document ID: US9437266B2 - Status: Granted - Kind: B2 - Application number: 13/675,923 - Filed: 2012-11-13 - Published: 2014-05-15 - Granted: 2016-09-06 - Earliest claimed: 2012-11-13 - Assignees: Macronix International Co., Ltd. - Applicants: Feng-Ming Lee; Yu-Yu Lin; Ming-Hsiu Lee - Inventors: Feng-Ming Lee; Yu-Yu Lin; Ming-Hsiu Lee - Web page: https://patentgrep.com/patent/US9437266B2 ## CPC - G11C 11/00: Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G11C14/00 - G11C21/00 take precedence) - H10N 70/245: {the species being metal cations, e.g. programmable metallization cells} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - H10N 70/8416: {adapted for supplying ionic species} - H10N 70/883: {Oxides or nitrides} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates. ## Claims ### Claim 1 A memory device, comprising a programmable metallization cell including: a first electrode and a second electrode; a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes, the ion-supplying layer containing a source of ions of a material suitable for formation of conductive bridges through the dielectric layer; and circuitry to apply, in a set operation, a first bias condition having a polarity between the first and second electrodes to cause current between the first and second electrodes having a direction to induce creation of conducting bridges within the dielectric layer, and to apply in a reset operation, a second bias condition having said polarity to cause current between the first and second electrodes having said direction to induce disintegration of bridges in the dielectric layer. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the dielectric layer comprises a material or materials supporting electrolytic formation of conducting bridges therethrough using ions from the ion-supplying layer. ### Claim 3 The memory device of 1, wherein the conductive ion-barrier layer comprises a material to block ion diffusion from the ion-supplying layer to the dielectric layer during the second bias condition, while allowing sufficient ion diffusion from the ion-supplying layer to the dielectric layer for formation of conductive bridges during the first bias condition. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the conductive ion-barrier layer comprises a nitrogen-containing conductive material. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the conductive ion-barrier layer comprises a metal nitride. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the ion-supplying layer comprises a source of copper ions. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the ion-supplying layer comprises a source of silver ions. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the ion-supplying layer comprises a material including copper and tellurium. ### Claim 9 (depends on 1) The memory device of claim 1, wherein the ion-supplying layer comprises a material including a chalcogenide and at least one of copper and silver. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the memory device includes a plurality of cells, including said programmable metallization cell, configured in a cross-point array. ### Claim 11 (depends on 1) The memory device of claim 1, wherein the dielectric layer comprises one or more materials selected from a group including dielectric oxides and dielectric nitrides, the conductive ion-barrier layer comprises one or more materials from a group including metal nitrides, and the ion-supplying layer comprises one or more materials selected from a group including copper or silver containing chalcogenides. ### Claim 12 An integrated circuit, comprising: a plurality of bit lines and a plurality of word lines; an array of memory cells and a corresponding array of access devices, coupled to the plurality of bit lines and the plurality of word lines, the memory cells in the array respectively including a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between corresponding word lines and bit lines; and sense circuitry coupled to the array of memory cells, to sense whether a selected memory cell has a threshold below a read threshold; control circuitry coupled to the plurality of bit lines and the plurality of word lines to apply bias arrangements for operation of the memory cells, including: a read bias arrangement to sense a resistance state of a selected memory cell; a first write bias arrangement to induce the formation of a bridge in the dielectric layer of a first selected memory cell establishing a first resistance state in the first selected memory cell, the first write bias having a polarity between a word line and a bit line connect to the first selected memory cell and inducing a current having a direction through the first selected memory cell; and a second write bias arrangement to induce disintegration of a bridge in the dielectric layer of a second selected memory cell establishing a second resistance state in the second selected memory cell, the second write bias having a polarity between a word line and a bit line connect to the second selected memory cell and inducing a current having said direction through the second selected memory cell. ### Claim 13 (depends on 12) The integrated circuit of claim 12, wherein the array of access devices comprises one diode for each memory cell.