# US 9,437,265 B2 · Semiconductor device having shallow trench isolation and gate groove > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,265 B2 - Document ID: US9437265B2 - Status: Granted - Kind: B2 - Application number: 14/461,705 - Filed: 2014-08-18 - Published: 2015-02-26 - Granted: 2016-09-06 - Earliest claimed: 2013-08-26 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Shinya Iwasa; Migaku Kobayashi - Web page: https://patentgrep.com/patent/US9437265B2 ## CPC - G11C 8/14: Word line organisation; Word line lay-out - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - H10B 12/50: {Peripheral circuit region structures} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 89/10: Integrated device layouts - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate including first and second regions that have different conductivity types from each other; a shallow trench isolation region (STI) comprising a shallow trench extending continuously within the first and second regions and being filled with an insulative material; first and second active regions placed in respective first and second regions and being each surrounded by the STI; gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench, the gate groove having regions that overlap the STI; a gate electrode disposed in the gate groove, the gate electrode being over the insulative material in regions where the gate groove and the STI overlap; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series. ### Claim 2 A semiconductor device comprising: a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench, the isolation region extending continuously over an intermediate region between the first and second active regions and extending continuously underneath the gate electrode in a region where the intermediate region and the gate electrode overlap; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series. ### Claim 3 (depends on 2) The semiconductor device according to claim 2 comprising: a plurality of memory cells; a plurality of sub-word lines electrically connected to the plurality of memory cells and to the logic circuit; and the logic circuit driving the plurality of memory cells via the sub-word line. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the first transistor includes first and second diffusion regions on both sides of a channel in the first active region, and the second transistor includes third and fourth diffusion regions on both sides of a channel in the second active region. ### Claim 5 (depends on 2) The semiconductor device according to claim 2 comprising an address signal line outputting a row address signal that selects a sub-word line in the same row from the plurality of sub-word lines and electrically connected to the gate electrode. ### Claim 6 (depends on 2) The semiconductor device according to claim 2 further comprising: a third active region placed in the second region, being surrounded by the isolation region, and isolated from the second active region; another gate groove placed in the second region including the third active region and the isolation region, being shallower than the isolation region and isolated from the gate groove; a third transistor placed in the second region and having a second gate electrode buried in a lower portion of the another gate groove; and the logic circuit having the second and third transistors connected in parallel. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the third transistor includes thirty-first and thirty-second diffusion regions on both sides of a channel in the third active region. ### Claim 8 (depends on 6) The semiconductor device according to claim 6 comprising a sub-word line non-selection signal line outputting a signal that deselects a sub-word line in the same column out of the plurality of sub-word lines and electrically connected to the second gate electrode. ### Claim 9 (depends on 8) The semiconductor device according to claim 8 comprising: a sub-word line selection signal line outputting a column address signal that selects a sub-word line in the same column from the plurality of sub-word lines and electrically connected to the eleventh diffusion region; and a reference potential line supplying a reference potential that sets the plurality of sub-word lines to a low level and electrically connected to each of the twenty-first and thirty-first diffusion regions, wherein all of the twelfth, twenty-second, and thirty-second diffusion regions are electrically connected to corresponding sub-word lines out of the plurality of sub-word lines. ### Claim 10 A semiconductor device comprising: a semiconductor substrate including first and second regions having first and second conductivity types, respectively; a shallow trench isolation (STI) region, a trench of the STI extending in each of the first and second regions and being filled with an insolating material; first and second active regions placed in respective first and second regions and each surrounded by the isolation material within the STI region; a gate electrode buried in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate electrode being over the isolation material of the STI in regions where the gate groove and STI overlap; and a cap insulating film buried in an upper portion of the gate groove and covering an upper surface of the gate electrode. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the gate electrode has a circular part formed in a circular shape on the first active region. ### Claim 12 A semiconductor device comprising: a semiconductor substrate including first and second regions having first and second conductivity types, respectively; an isolation region extending in each of the first and second regions; first and second active regions placed in respective first and second regions and each surrounded by the isolation region; a gate electrode buried in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region the gate electrode having a circular part formed in a circular shape on the first active region a portion of the circular part being placed on the isolation region; and a cap insulating film buried in an upper portion of the gate groove and covering an upper surface of the gate electrode. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the first active region is a plurality of first active regions formed in a band shape in a first direction, and the gate electrode has a circular part formed in a circular shape on each of the first active regions and is continuously connected to the circular part adjacent in a direction different from the first direction on the isolation region. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein the first active region has an eleventh diffusion region in a region outside the circular part and has a twelfth diffusion region in a region within the circular part. ### Claim 15 (depends on 14) The semiconductor device according to claim 14 further comprising first and second contact plugs electrically connected to the eleventh and twelfth diffusion regions, respectively. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein one or both of the first and second contact plugs is/are also disposed on the gate groove and in contact with the cap insulating film. ### Claim 17 (depends on 15) The semiconductor device according to claim 15, wherein the cap insulating film has a portion positioned higher than an upper surface of the eleventh and twelfth diffusion regions, an interlayer insulating film buried in an opening of the cap insulating film is provided, the interlayer insulating film has first and second holes leading to the eleventh and twelfth diffusion regions, respectively, and the first and second contact plugs are buried in the first and second holes, respectively. ### Claim 18 (depends on 15) The semiconductor device according to claim 15 comprising: the second active region having twenty-first and twenty-second diffusion regions on both sides of a channel along the gate groove; and third and fourth contact plugs electrically connected to the twenty-first and twenty-second diffusion regions, respectively. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein one or both of the third and fourth contact plugs is/are disposed on the gate groove and in contact with the cap insulating film. ### Claim 20 (depends on 18) The semiconductor device according to claim 18, wherein the cap insulating film has a portion positioned higher than an upper surface of the twenty-first and twenty-second diffusion regions, an interlayer insulating film buried in an opening of the cap insulating film is provided, the interlayer insulating film has third and fourth holes leading to the twenty-first and twenty-second diffusion regions, respectively, and the third and fourth contact plugs are buried in the third and fourth holes, respectively. ### Claim 21 A semiconductor device comprising: a semiconductor substrate including first and second regions that have different conductivity types from each other; a shallow trench isolation region (STI) having a trench extending over the first and second regions and being filled with an insulative material; and a conductive material disposed in a groove that extends continuously over the first and second regions, the groove and the STI having overlapping regions, the insulative material of the STI being beneath the conductive material in the overlapping regions. ### Claim 22 (depends on 21) The semiconductor device according to claim 21, further comprising: a plurality of memory cells placed in the second region, the conductive material as a sub-word line extending over the plurality of memory cells; and an additional conductive material connecting to the conductive material over the second region.