# US 9,437,264 B2 · Memory operation latency control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,264 B2 - Document ID: US9437264B2 - Status: Granted - Kind: B2 - Application number: 15/055,329 - Filed: 2016-02-26 - Published: 2016-06-23 - Granted: 2016-09-06 - Earliest claimed: 2013-03-14 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Chun-Hsiung Hung; Han-Sung Chen; Ming-Chao Lin - Web page: https://patentgrep.com/patent/US9437264B2 ## CPC - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/30: Power supply circuits - G11C 2207/2272: Latency related aspects - G11C 2207/2281: Timing of a read operation - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage. ## Claims ### Claim 1 A method of operating an integrated circuit with memory, comprising: performing a first operation on a memory array; and in response to a read command sequence after said first operation, performing a first read operation characterized by a first latency or performing a second read operation characterized by a second read latency, the first read operation being performed if a time delay between the first operation and the read command sequence is not less than a timing parameter, the second read operation being performed if said time delay is less than the timing parameter. ### Claim 2 (depends on 1) The method of claim 1, including measuring a time between an end of the first operation and initiation of the read command sequence to determine the time delay. ### Claim 3 (depends on 1) The method of claim 1, wherein the end of the first operation used to determine the time delay is indicated by a toggle of a chip enable signal. ### Claim 4 (depends on 3) The method of claim 3, wherein an initiation of the read command sequence used to determine the time delay is indicated by a subsequent toggle of said chip enable signal. ### Claim 5 (depends on 1) The method of claim 1, wherein the first read operation includes a first sequence of steps and the second read operation includes a second sequence of steps that is different from the first sequence of steps. ### Claim 6 (depends on 5) The method of claim 5, wherein the first sequence includes a charge pump setup, a word line setup, and sense amplifier sensing. ### Claim 7 (depends on 5) The method of claim 5, wherein the second sequence does not include a charge pump setup, and includes a word line setup and sense amplifier sensing. ### Claim 8 (depends on 5) The method of claim 5, wherein the second sequence does not include a charge pump setup and a word line setup, and includes sense amplifier sensing. ### Claim 9 An integrated circuit, comprising: a memory array; and control circuitry coupled to the memory array, wherein the control circuitry: in response to a read command sequence, performing a first read operation characterized by a first latency or performing a second read operation characterized by a second read latency, the first read operation being performed if the time delay between a previous operation and the read command sequence is less than a timing parameter, the second read operation being performed if said time delay is not less than the timing parameter. ### Claim 10 (depends on 9) The integrated circuit of claim 9, including a timer measuring a time between an end of the previous operation and initiation of the read command sequence to determine the time delay. ### Claim 11 (depends on 9) The integrated circuit of claim 9, wherein the timer is responsive to a toggle of a chip enable signal to indicate an end of the previous operation. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the timer is responsive to a subsequent toggle of the chip enable signal to indicate initiation of the read command sequence. ### Claim 13 (depends on 9) The integrated circuit of claim 9, wherein the first read operation includes a first sequence of steps and the second read operation includes a second sequence of steps that is different from the first sequence of steps. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the first sequence includes a charge pump setup, a word line setup, and sense amplifier sensing. ### Claim 15 (depends on 13) The integrated circuit of claim 13, wherein the second sequence does not include a charge pump setup, and includes a word line setup and sense amplifier sensing. ### Claim 16 (depends on 13) The integrated circuit of claim 13, wherein the second sequence does not include a charge pump setup and a word line setup, and includes sense amplifier sensing. ### Claim 17 A method of operating an integrated circuit with memory, comprising: performing a first read operation on a memory array in response to a first read command sequence initiated at a first time, the first read operation characterized by a first read latency; and in response to a second read command sequence initiated at a second time, the second time occurring after the first read operation terminates, performing a second read operation characterized by a second read latency less than the first read latency, if a time difference between an end of the first read operation and the second time is less than a timing parameter, else performing said first read operation.