# US 9,437,262 B2 · Memory controller and associated signal generating method

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- Number: US 9,437,262 B2
- Document ID: US9437262B2
- Status: Granted
- Kind: B2
- Application number: 14/311,502
- Filed: 2014-06-23
- Published: 2014-12-25
- Granted: 2016-09-06
- Earliest claimed: 2013-06-25
- Assignees: MStar Semiconductor, Inc.
- Applicants: MStar Semiconductor, Inc.
- Inventors: Zong-Han Wu; Chen-Nan Lin; Chung-Ching Chen; Yung Chang
- Web page: https://patentgrep.com/patent/US9437262B2

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.

## Claims

### Claim 1

A signal generating method of a memory controller, for controlling a memory module, comprising:
generating a first clock signal having a signal period of a unit time;
generating a command signal having a signal period of the unit time, wherein the command signal comprises a plurality of command groups each having a first command and a second command that are consecutive;
generating an address signal set having a signal period of twice of the unit time;
setting a first signal edge of the first clock signal to within a latching interval of the command signal;
setting a second signal edge of the first clock signal to within the latching interval of the command signal and a latching interval of the address signal set; and
controlling the memory module according to the command signal and the address signal.

### Claim 2 (depends on 1)

The signal generating method according to claim 1, for further controlling another memory module, comprising:
generating a second clock signal having a signal period of the unit time;
setting a first signal edge of the second clock signal to within the latching interval of the command signal; and
setting a second signal edge of the second clock signal to within the latching interval of the command signal and the latching interval of the address signal set.

### Claim 3 (depends on 2)

The signal generating method according to claim 2, wherein the memory module and the another memory module are double data rate (DDR) memory modules.

### Claim 4 (depends on 1)

The signal generating method according to claim 1, wherein the unit time is a period of the first clock signal.

### Claim 5 (depends on 1)

The signal generating method according to claim 1, wherein the address signal set comprises an address signal and a bank control signal.

### Claim 6 (depends on 1)

The signal generating method according to claim 1, wherein the first command is a no operation command.

### Claim 7 (depends on 1)

The signal generating method according to claim 1, wherein the second command is one of a no operation command, a bank bus pre-charge command, a drive bank bus command, a write command and a read command.

### Claim 8 (depends on 1)

The signal generating method according to claim 1, wherein the first signal edge of the first clock signal is outside the latching interval of the address signal set.

### Claim 9 (depends on 1)

The signal generating method according to claim 1, wherein the first signal edge and the second signal edge of the first clock signal are both rising edges of the first clock signal.

### Claim 10 (depends on 1)

The signal generating method according to claim 1, wherein the address signal set is one of an address signal and a bank control signal.

### Claim 11 (depends on 10)

The signal generating method according to claim 10, wherein when the address signal set is the address signal, a signal period of the bank control signal is a unit time, and the first signal edge and the second signal edge of the first clock signal are set to within a latching interval of the bank control signal.

### Claim 12 (depends on 10)

The signal generating method according to claim 10, wherein when the address signal set is the bank control signal, a signal period of the address signal is a unit time, and the first signal edge and the second signal edge of the first clock signal are set to a latching interval of the address signal.

### Claim 13

A memory controller, connectable to a memory module, comprising:
a clock generating unit, configured to generate a first clock signal having a signal period of a unit time to the memory module;
a control signal translating unit, configured to generate a command signal having a signal period of the unit time to the memory module, wherein the command signal comprises a plurality of command groups each having a first command and a second command that are consecutive; and
an address translating unit, configured to generate an address signal set having a signal period of twice of the unit time to the memory module;
wherein, the clock generating unit sets a first signal edge of the first clock signal to within a latching interval of the command signal, and sets a second signal edge of the first clock signal to within the latching interval of the command signal and a latching interval of the address signal set.

### Claim 14 (depends on 13)

The memory controller according to claim 13, further connectable to another memory module, wherein the clock generating unit generates a second clock signal having a signal period of the unit time, sets a first signal edge of the second clock signal to within the latching interval of the command signal, and sets a second signal edge of the second clock signal to within the latching interval of the command signal and the latching interval of the address signal set.

### Claim 15 (depends on 14)

The memory controller according to claim 14, wherein the memory module and the another memory module are both DDR modules.

### Claim 16 (depends on 13)

The memory controller according to claim 13, wherein the unit time is a period of the first clock signal.

### Claim 17 (depends on 13)

The memory controller according to claim 13, wherein the address signal set comprises an address signal and a bank control signal.

### Claim 18 (depends on 13)

The memory controller according to claim 13, wherein the first command is a no operation command.

### Claim 19 (depends on 13)

The memory controller according to claim 13, wherein the second command is one of a no operation command, a bank bus pre-charge command, a drive bank bus command, a write command and a read command.

### Claim 20 (depends on 13)

The memory controller according to claim 13, wherein the first signal edge of the first clock signal is outside the latching interval of the address signal set.