Reprogrammable logic device resistant to radiations
AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, Centre National De La Recherche Scientifique
InventorsGuillaume Prenat, Olivier Goncalves
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Abstract
The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell comprising first and second resistance-switching elements, each being programmable so as to have one of a first and of a second resistance value representative of the refresh data; and a read-write circuit adapted for periodically refreshing the configuration data on the basis of the refresh data.
Claims16
A reprogrammable logic device comprising a plurality of tiles, each tile comprising:
- at least one logic block (108) adapted to perform a logic function, one or more interconnections of the logic block and the logic function applied by the logic block being configurable by configuration data stored by one or more volatile memory cells (322) storing configuration data;
- and
- a memory (116) comprising:
- a plurality of non-volatile memory cells (402) storing refresh data, each non-volatile memory cell comprising first and second resistance switching elements (520, 522) each programmable to have one of first and second resistance values (Rmin, Rmax) representative of said refresh data;
- and
- read-write circuitry (408) adapted to periodically refresh said configuration data based on said refresh data at intervals of between 1 and 100 milliseconds.
A method of refreshing a reprogrammable device comprising a plurality of tiles (102), each tile comprising at least one logic block (108) adapted to perform a logic function, comprising one or more inputs coupled to one or more volatile memory cells (322) storing configuration data, the method comprising:
- periodically refreshing, at intervals of between 1 and 100 milliseconds, said configuration data based on refresh data stored in non-volatile memory cells (402) of a memory (116), wherein each non-volatile memory cell comprises first and second resistance switching elements (520, 522) each programmable to have one of first and second resistance values (Rmin, Rmax).
Dependencies are inferred from the claim text.