# US 9,437,259 B2 · Memory system including memory chips having serially and parallel arranging input/output

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- Number: US 9,437,259 B2
- Document ID: US9437259B2
- Status: Granted
- Kind: B2
- Application number: 14/857,511
- Filed: 2015-09-17
- Published: 2016-01-07
- Granted: 2016-09-06
- Earliest claimed: 2013-05-31
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Heat-Bit Park; Kang-Seol Lee
- Web page: https://patentgrep.com/patent/US9437259B2

## CPC

- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/106: {Data output latches}
- G11C 7/1087: {Data input latches}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 29/1201: {comprising I/O circuitry}
- G11C 2207/107: Serial-parallel conversion of data or prefetch
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.

## Claims

### Claim 1

A memory system comprising:
a first memory chip including first to Nth cell arrays, each including a plurality of memory cells;
a second memory chip, stacked on the first memory chip, including first to Nth cell arrays, each including a plurality of memory cells, and to be stacked on the first memory chip; and
one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays of the first memory chip and to the first to Nth cell arrays of the second memory chip, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays of the first memory chip and to the first to Nth cell arrays of the second memory chip;
the first to Nth data output units are configured to serially arrange data received from corresponding cell arrays of the first to Nth cell arrays of the first memory chip and from corresponding cell arrays of the first to Nth cell arrays of the second memory chip, and output the serially-arranged data to the corresponding first to Nth data input/output pads; and
the first to Nth data input units are configured to parallel-arrange data inputted through the corresponding first to Nth data input/output pads, and input the parallel-arranged data to the corresponding cell arrays of the first to Nth cell arrays of the first memory chip and to the corresponding cell arrays of the first to Nth cell arrays of the second memory chip.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the one or more first to Nth data input/output pads are disposed on the first memory chip, and wherein the one or more first to Nth data input/output pads of the first memory chip are disposed adjacent to corresponding cells arrays from among the first to Nth cell arrays of the first memory chip.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein:
a Kth cell array (1≦K≦M), of the first to Nth cell arrays of the first memory chip, and a Kth cell array, of the first to Nth cell arrays of the second memory chip, are configured to be identical to each other in relative positions within the first memory chip and second memory chip, respectively; and
the first to Nth cell arrays of the second memory chip are configured to be coupled, by through vias, to corresponding ones of the one or more data input/output pads, from among the one or more first to Nth data input/output pads.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein:
each of the first to Nth cell arrays, of the first memory chip, is configured to include first to Mth sub-cell arrays including a plurality of memory cells, and
each of the first to Nth cell arrays, of the second memory chip, is configured to include first to Mth sub-cell arrays including a plurality of memory cells; and
the first to Mth sub-cell arrays, of the first to Nth cell arrays of the first memory chip, and the first to Mth sub-cell arrays, of the first to Nth cell arrays of the second memory chip, correspond to first to Mth banks of sub-cells, wherein each of the first to Mth banks of sub-cells are identified by a respective bank address.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein:
a first group is configured to:
include first to Lth sub-cell arrays (1≦L≦M), from among the first to Mth sub-cell arrays of the first to Nth cell arrays of the first memory chip, and
include (L+1)th to Mth sub-cell arrays (1≦L≦M), from among the first to Mth sub-cell arrays of the first to Nth cell arrays of the second memory chip and;
a second group is configured to:
include (L+1)th to Mth sub-cell arrays (1≦L≦M), from among the first to Mth sub-cells arrays of the first to Nth cell arrays of the first memory chip, and
include first to Lth sub-cell arrays, from among the first to Mth sub-cell arrays of the first to Nth cell arrays of the second memory chip,
wherein, during a data input/output operation of the first group, in response to a command accompanied with input/output of data and an address including the bank address, data is inputted to/outputted from selected memory cells of a sub-cell array which is selected from among the first to Lth sub-cell arrays of the first memory chip and the (L+1)th to Mth sub-cell arrays of the second memory chip, and wherein, during a data input/output operation of the second group, in response to a command accompanied with input/output of data and an address including the address, data is inputted to/outputted from selected memory cells of a sub-cell array which is selected from among the first to Lth sub-cell arrays of the second memory chip and the (L+1)th to Mth sub-cell arrays of the first memory chip.