# US 9,437,258 B2 · Data readout circuit of a storage device for read-out operation for preventing erroneous writing into a data storage element and reading out of the data correctly

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- Number: US 9,437,258 B2
- Document ID: US9437258B2
- Status: Granted
- Kind: B2
- Application number: 14/844,921
- Filed: 2015-09-03
- Published: 2016-03-10
- Granted: 2016-09-06
- Earliest claimed: 2014-09-09
- Assignees: Sii Semiconductor Corporation
- Applicants: Seiko Instruments Inc.
- Inventors: Makoto Mitani; Kotaro Watanabe
- Web page: https://patentgrep.com/patent/US9437258B2

## CPC

- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/067: {Single-ended amplifiers}
- G11C 7/106: {Data output latches}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Provided is a data readout circuit capable of, even when a high voltage is applied during data read-out operation, preventing erroneous writing of the data and reading out the data correctly. The data readout circuit includes: a non-volatile storage element; a latch circuit including: an input inverter; an output inverter; and a MOS transistor; a first MOS transistor connected between the non-volatile storage element and the latch circuit; a second MOS transistor connected between the latch circuit and the first power supply terminal; a first bias circuit configured to bias a gate of the first MOS transistor; and a second bias circuit configured to bias the MOS transistor in the latch circuit, each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.

## Claims

### Claim 1

A data readout circuit, comprising:
a non-volatile storage element;
a latch circuit comprising:
an input inverter;
an output inverter; and
a third MOS transistor connected between the output inverter and a first power supply terminal,
the latch circuit being configured to hold data in the non-volatile storage element;
a first MOS transistor directly connected to the non-volatile storage element and directly connected to the latch circuit;
a second MOS transistor directly connected to the latch circuit and the first power supply terminal;
a first bias circuit configured to bias a gate of the first MOS transistor; and
a second bias circuit configured to bias the third MOS transistor in the latch circuit,
each of the first bias circuit and the second bias circuit being configured to output a predetermined bias voltage when the data in the non-volatile storage element is read out.

### Claim 2 (depends on 1)

A data readout circuit according to claim 1, further comprising:
a first capacitor connected between an output terminal of the first bias circuit and a second power supply terminal; and
a second capacitor connected between an output terminal of the second bias circuit and the first power supply terminal.

### Claim 3 (depends on 1)

A data readout circuit according to claim 1, wherein the data in the non-volatile storage element is read out from an output terminal of the input inverter in the latch circuit.

### Claim 4 (depends on 2)

A data readout circuit according to claim 2, wherein the data in the non-volatile storage element is read out from an output terminal of the input inverter in the latch circuit.