# US 9,437,256 B2 · Data shifting > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,256 B2 - Document ID: US9437256B2 - Status: Granted - Kind: B2 - Application number: 14/660,219 - Filed: 2015-03-17 - Published: 2015-07-02 - Granted: 2016-09-06 - Earliest claimed: 2013-09-19 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Timothy B. Cowles; Steven M. Bodily - Web page: https://patentgrep.com/patent/US9437256B2 ## CPC - G11C 7/065: {Differential amplifiers of latching type} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/08: Control thereof - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1036: {using data shift registers} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 8/10: Decoders - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers - G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier - G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense line of an array, a first isolation device located between the first memory cell and first sensing circuitry corresponding thereto, and a second isolation device located between the first memory cell and second sensing circuitry corresponding to a second sense line. The first and the second isolation devices are operated to shift data in the array without transferring the data via an input/output line of the array. ## Claims ### Claim 1 An apparatus, comprising: a first memory cell and a second memory cell; a first sense line coupled to the first memory cell; a second sense line coupled to the second memory cell; a first transistor device including a first node coupled to the first sense line; a second transistor including a first node coupled to the second sense line; a third transistor coupled between the first sense line and the second sense line; a first sensing circuitry coupled to a second node of the first transistor; a second sensing circuitry coupled to a second node of the second transistor; and a fourth transistor coupled between the first node of the first transistor and the second node of the second transistor and including a control node coupled to a second control node supplying a second control signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the third transistor is coupled between the second node of the first transistor and the first node of the second transistor. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein a control node of the third transistor is coupled to a first control node supplying a first control signal. ### Claim 4 A method comprising: reading out data from a first memory cell to a first sense line while disconnecting the first sense line from a second sensing circuitry to which the first sense line is coupled; connecting the first sense line to a first sensing circuitry so that the first sensing circuitry amplifies the data on the first sense line to produce amplified data; disconnecting the first sense line from the first sensing circuitry; and storing the amplified data into a second memory cell through a second sense line coupled to the second memory cell. ### Claim 5 (depends on 4) The method of claim 4, wherein the storing the amplified data into the second memory cell includes storing the amplified data into an accumulator. ### Claim 6 (depends on 4) The method of claim 4, wherein the amplified data is stored in the second memory cell while the first memory cell is being accessed. ### Claim 7 (depends on 4) The method of claim 4, wherein the second sensing circuitry is coupled to the first sense line via a first transistor having a first node coupled to the first sense line and a second node coupled to the second sense line. ### Claim 8 (depends on 7) The method of claim 7, wherein disconnecting the first sense line from the first sensing circuitry includes enabling a second transistor having a first node coupled to the first node of the first transistor. ### Claim 9 An apparatus, comprising: a first word line; first and second sense lines each intersecting the first word line; first and second memory cells disposed at an intersection of the first word line and the first sense line and an intersection of the first word line and the second sense line; first and second sensing circuits; a first switch coupled between the first sense line and the first sensing circuit; a second switch coupled between the second sense line and the second sensing circuit; and a third switch coupled between the first sensing circuit and the second sense line. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the third switch is turned OFF when each of the first and second switches is turned ON, and the third switch is turned ON when each of the first and second switch is turned OFF. ### Claim 11 (depends on 9) The apparatus of claim 9, further comprising a fourth switch coupled between the first sensing circuit and the second sensing circuit. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein each of the third and fourth switches is turned OFF when each of the first and second switches is turned ON, and each of the third and fourth switches is turned ON when each of the first and second switches is turned OFF. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the third switch is coupled to the first sensing line through the first switch. ### Claim 14 (depends on 11) The apparatus of claim 11, wherein the fourth switch is coupled to the second sensing line through the second switch. ### Claim 15 (depends on 9) The apparatus of claim 9, further comprising first and second accumulators provided for the first and second sensing circuits, respectively. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein the first and second accumulators are formed on pitch with memory cells of an array comprising the first and second memory cells. ### Claim 17 An apparatus, comprising: a first memory cell and a second memory cell; a first sense line coupled to the first memory cell; a second sense line coupled to the second memory cell; a first transistor device including a first node coupled to the first sense line; a second transistor including a first node coupled to the second sense line; a third transistor coupled between the first sense line and the second sense line; a first sensing circuitry coupled to a second node of the first transistor; a second sensing circuitry coupled to a second node of the second transistor; and wherein a control node of the first transistor and a control node of the second transistor are coupled to a third control node supplying a control signal. ### Claim 18 An apparatus, comprising: a first memory cell and a second memory cell; a first sense line coupled to the first memory cell; a second sense line coupled to the second memory cell; a first transistor device including a first node coupled to the first sense line; a second transistor including a first node coupled to the second sense line; a third transistor coupled between the first sense line and the second sense line; a first sensing circuitry coupled to a second node of the first transistor; a second sensing circuitry coupled to a second node of the second transistor; and wherein the first memory cell and the second memory cell are coupled to a same first word line. ### Claim 19 An apparatus, comprising: a first memory cell and a second memory cell; a first sense line coupled to the first memory cell; a second sense line coupled to the second memory cell; a first transistor device including a first node coupled to the first sense line; a second transistor including a first node coupled to the second sense line; a third transistor coupled between the first sense line and the second sense line; a first sensing circuitry coupled to a second node of the first transistor; a second sensing circuitry coupled to a second node of the second transistor; and a first accumulator coupled to the first sense line to temporarily store a data value on the first sense line.