# US 9,437,253 B2 · Memory devices having data lines included in top and bottom conductive lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,253 B2 - Document ID: US9437253B2 - Status: Granted - Kind: B2 - Application number: 14/330,737 - Filed: 2014-07-14 - Published: 2014-10-30 - Granted: 2016-09-06 - Earliest claimed: 2012-08-21 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Toru Tanzawa - Web page: https://patentgrep.com/patent/US9437253B2 ## CPC - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 8/14: Word line organisation; Word line lay-out - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different levels of the apparatuses and arranged in memory cell strings. At least a portion of the first set of conductive lines is configured as a first set of data lines. At least a portion of the second set of conductive lines is configured as a second set of data lines. Each of the memory strings is coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines. Other embodiments including additional apparatuses and methods are described. ## Claims ### Claim 1 An apparatus comprising: a first set of conductive lines located on a first level of the apparatus; a second set of conductive lines located on a second level of the apparatus; memory cell strings, each of the memory strings coupled to a respective conductive line in the first set of conductive lines and a respective conductive line in the second set of conductive lines; and a module configured to obtain information from a first portion of the memory cell strings through a portion of the first set of conductive lines and to obtain information from a second portion of the memory cell strings through a portion of the second set of conductive lines. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the module is configured to couple another portion of the first set of conductive lines to a common node during an operation of the apparatus. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the module is configured to couple another portion of the second set of conductive lines to the common node during the operation of the apparatus. ### Claim 4 (depends on 1) The apparatus of claim 1, the module is configured to concurrently obtain information from the first and second portions of the memory cell strings. ### Claim 5 An apparatus comprising: a memory cell set including memory cells; a first set of data lines located on a first level of the apparatus; a second set of data lines located on a second level of the apparatus; and a module configured to perform a first operation to obtain information from a first portion of the memory cells through the first set of data lines and to obtain information from a second portion of the memory cells through the second set of data lines, and a second operation to store information in the first portion of the memory cells through the first set of data lines and to store information in the second portion of the memory cells through the second set of data lines. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the memory cells are arranged in a same row. ### Claim 7 (depends on 5) The apparatus of claim 5, further comprising: additional memory cells arranged in an additional row; a first access line shared by the memory cells; and a second access line shared by the additional memory cells, wherein the module is configured to obtain information from a first portion of the additional memory cells through the first set of data lines and to obtain information from a second portion of the additional memory cells through the second set of data lines. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the memory cells and the additional memory cells are located in a same level of the apparatus. ### Claim 9 A method comprising: selecting a first memory cell string in an operation of a device, the first memory cell string coupled to a first conductive line in a first set of conductive lines located on a first level of the device and coupled to a first conductive line in a second set of conductive lines located on a second level of the device, wherein at least one conductive line in the first set of conductive lines is configured as a data line; and selecting a second memory cell string in the operation of a device, the second memory cell string coupled to a second conductive line in a first set of conductive lines and coupled to a second conductive line in the second set of conductive lines, wherein at least one conductive line in the second set of conductive lines is configured as a data line. ### Claim 10 (depends on 9) The method of claim 9, wherein the operation includes a read operation. ### Claim 11 (depends on 9) The method of claim 9, wherein the operation includes a write operation. ### Claim 12 (depends on 9) The method of claim 9, further comprising: obtaining information from a first memory cell in the first memory cell string through the first conductive line in the first set of conductive lines; and obtaining information from a second memory cell in the second memory cell string through the second conductive line in the second set of conductive lines. ### Claim 13 (depends on 11) The method of claim 11, wherein first and second memory cells share a same access line. ### Claim 14 (depends on 12) The method of claim 12, wherein obtaining the information from the first memory cell and obtaining the information from the second memory cell are performed concurrently. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the portion of the first set of conductive lines is configured as a portion of a set of data lines. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the portion of the second set of conductive lines is configured as a portion of another set of data lines. ### Claim 17 (depends on 2) The apparatus of claim 2, wherein the common node is configured to couple to ground potential. ### Claim 18 (depends on 1) The apparatus of claim 1, further comprising sense circuits, each of the sense circuits coupled to a respective conductive in the portions of the first and second sets of conductive lines. ### Claim 19 (depends on 1) The apparatus of claim 1, wherein the portion of the first set of conductive lines includes conductive material formed in a substrate, and the portion of the second set of conductive lines includes conductive material formed over the substrate. ### Claim 20 (depends on 1) The apparatus of claim 1, wherein the portion of the first set of conductive lines includes conductive material formed over a substrate, and the portion of the second set of conductive lines includes conductive material formed over the substrate.