# US 9,437,252 B2 · Stack bank type semiconductor memory apparatus capable of improving alignment margin

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- Number: US 9,437,252 B2
- Document ID: US9437252B2
- Status: Granted
- Kind: B2
- Application number: 14/829,791
- Filed: 2015-08-19
- Published: 2016-01-28
- Granted: 2016-09-06
- Earliest claimed: 2007-11-09
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Seung Wook Kwak; Sang Hoon Shin; Keun Soo Song
- Web page: https://patentgrep.com/patent/US9437252B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 8/10: Decoders
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory apparatus is capable of improving the alignment margin for a bank and sufficiently ensuring a space for forming a global input/output line. The semiconductor memory apparatus includes a stack bank structure having at least two sub-banks continuously stacked without disconnection of data signal lines, and a control block arranged at one side of the stack bank structure to simultaneously control column-related signals of the sub-banks.

## Claims

### Claim 1

A semiconductor memory apparatus comprising:
a plurality of stack bank structures, the plurality of stack bank structures being spaced apart from each other at a predetermined interval and including a plurality of sub-banks;
a plurality of control blocks, wherein each control block configured to control all column-related signals of the plurality of sub-banks constituting each stack bank structure; and
a plurality of global input/output lines arranged between the stack bank structures,
wherein each of the plurality of control blocks includes an address control block and an Input/Output control block, the address control block is arranged between the plurality of sub banks constituted in each of the plurality of stack bank structures, the Input/Output control block is arranged at one side of each of the plurality of stack bank structures, and the address control block includes a main decoder and a predecoder.

### Claim 2 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein the plurality of sub-banks are continuously stacked without disconnection of signal lines.

### Claim 3 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein a predetermined number of global input/output lines are provided to each stack bank structure, and wherein the global input/output lines are used for data input/output of the plurality of sub-banks constituting the stack bank structure.

### Claim 4 (depends on 3)

The semiconductor memory apparatus of claim 3, wherein the global input/output lines are arranged between the control blocks in parallel to the control blocks.