# US 9,437,168 B2 · Gate driving circuit and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,437,168 B2 - Document ID: US9437168B2 - Status: Granted - Kind: B2 - Application number: 14/535,066 - Filed: 2014-11-06 - Published: 2015-12-03 - Granted: 2016-09-06 - Earliest claimed: 2014-05-27 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Yong-Koo Her - Web page: https://patentgrep.com/patent/US9437168B2 ## CPC - G09G 3/035: {for flexible display surfaces} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3225: using an active matrix - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/04: Partial updating of the display screen - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A gate driving circuit and display device including the same are disclosed. In one aspect, the gate driving circuit includes a plurality of stages, each stage including a first input portion configured to apply an input signal to a first node based on a first clock signal, a first output portion configured to output a second clock signal as a gate output signal based on a first node signal applied to the first node, a second input portion configured to apply the first clock signal to a second node based on the first node signal, a second output portion configured to output a first voltage as the gate output signal based on a second node signal applied to the second node, and an output control portion configured to activate the first output portion based on an output control signal. ## Claims ### Claim 1 A gate driving circuit for a display device, comprising: a plurality of stages configured to respectively output a plurality of gate output signals, each stage comprising: a first input portion configured to apply an input signal to a first node based at least in part on a first clock signal; a first output portion configured to output a second clock signal as a gate output signal based at least in part on a first node signal applied to the first node; a second input portion configured to apply the first clock signal to a second node based at least in part on the first node signal; a second output portion configured to output a first voltage as the gate output signal based at least in part on a second node signal applied to the second node; and an output control portion configured to activate the first output portion based at least in part on an output control signal, wherein the display device comprises: a flexible display panel electrically connected to the gate driving circuit; a timing controller electrically connected to the gate driving circuit; a flexibility detector configured to i) detect a non-display region of the flexible display panel and ii) transmit non-display region information relating to the non-display region to the timing controller, wherein the timing controller is configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level in non-display stages corresponding to the non-display region using the non-display region information, and wherein the first and second logic levels are respectively logical high and logical low levels. ### Claim 2 (depends on 1) The gate driving circuit of claim 1, wherein an (N)th stage represents a selected stage among the stages, and wherein the (N)th stage further includes: a stabilizing portion configured to substantially stabilize the (N)th gate output signal based at least in part on the second node signal and the second clock signal. ### Claim 3 (depends on 2) The gate driving circuit of claim 2, wherein the stabilizing portion includes first and second stabilizing transistors connected to each other in series, wherein the first stabilizing transistor includes a gate electrode connected to the second node, a source electrode to which the first voltage is applied, and a drain electrode connected to a source electrode of the second stabilizing transistor, and wherein the second stabilizing transistor includes a gate electrode to which the second clock signal is applied, the source electrode connected to the drain electrode of the first stabilizing transistor, and a drain electrode connected to the first node. ### Claim 4 (depends on 1) The gate driving circuit of claim 1, wherein an (N)th stage represents a selected stage among the stages, and wherein the (N)th stage further includes: a holding portion configured to maintain the second node signal based at least in part on the first clock signal. ### Claim 5 A display device comprising: a display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, and a plurality of pixels respectively connected to a selected one of the gate lines and a selected one of the data lines; a data driver configured to transmit a plurality of data signals to the data lines, respectively; a gate driver including a plurality of stages and configured to transmit a plurality of gate output signals to the gate lines, respectively; and a timing controller configured to control the gate driver and the data driver, wherein each stage includes: a first input portion configured to apply an input signal to a first node based at least in part on a first clock signal; a first output portion configured to output a second clock signal as a gate output signal based at least in part on a first node signal applied to the first node; a second input portion configured to apply the first clock signal to a second node based at least in part on the first node signal; a second output portion configured to output a first voltage as the gate output signal based at least in part on a second node signal applied to the second node; and an output control portion configured to activate the first output portion based at least in part on an output control signal, wherein the display panel is flexible; wherein the display device further comprises a flexibility detector configured to i) detect a non-display region of the flexible display panel and ii) transmit non-display region information relating to the non-display region to the timing controller, wherein the timing controller is further configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level in non-display stages corresponding to the non-display region using the non-display region information, and wherein the first and second logic levels are respectively logical high and logical low levels. ### Claim 6 (depends on 5) The display device of claim 5, wherein the display panel is foldable. ### Claim 7 A display device, comprising: a display panel including a plurality of gate lines, a plurality of data lines crossing the gate lines, and a plurality of pixels respectively connected to a selected one of the gate lines and a selected one of the data lines; a data driver configured to transmit a plurality of data signals to the data lines, respectively; a gate driver including a plurality of stages and configured to transmit a plurality of gate output signals to the gate lines, respectively; and a timing controller configured to control the gate driver and the data driver, wherein each stage includes: a first input portion configured to apply an input signal to a first node based at least in part on a first clock signal; a first output portion configured to output a second clock signal as a gate output signal based at least in part on a first node signal applied to the first node; a second input portion configured to apply the first clock signal to a second node based at least in part on the first node signal; a second output portion configured to output a first voltage as the gate output signal based at least in part on a second node signal applied to the second node; and an output control portion configured to activate the first output portion based at least in part on an output control signal, wherein the display panel is foldable, and wherein the timing controller is configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level in non-display stages corresponding to a non-display region of the foldable display panel when the display panel is folded, and wherein the first and second logic levels are respectively logical high and logical low levels. ### Claim 8 (depends on 5) The display device of claim 5, wherein the timing controller is further configured to output the output control signal having a first logic level and the first and second clock signals having a second logic level during a predetermined non-display period when image data included in the data signals is still image data, and wherein the first and second logic levels are respectively logical high and logical low levels. ### Claim 9 (depends on 5) The display device of claim 5, wherein an (N)th stage represents a selected stage among the stages, and wherein the (N)th stage further includes: a stabilizing portion configured to substantially stabilize the (N)th gate output signal based at least in part on the second node signal and the second clock signal. ### Claim 10 (depends on 9) The display device of claim 9, wherein the stabilizing portion includes first and second stabilizing transistors connected to each other in series, wherein the first stabilizing transistor includes a gate electrode connected to the second node, a source electrode to which the first voltage is applied, and a drain electrode connected to a source electrode of the second stabilizing transistor, and wherein the second stabilizing transistor includes a gate electrode to which the second clock signal is applied, the source electrode connected to the drain electrode of the first stabilizing transistor, and a drain electrode connected to the first node. ### Claim 11 (depends on 5) The display device of claim 5, wherein an (N)th stage represents a selected stage among the stages, and wherein the (N)th stage further includes: a holding portion configured to maintain the second node signal based at least in part on the first clock signal. ### Claim 12 (depends on 11) The display device of claim 11, wherein the holding portion includes a holding transistor, and wherein the holding transistor includes a gate electrode to which the first clock signal is applied, a source electrode to which a second voltage is applied, and a drain electrode connected to the second node. ### Claim 13 (depends on 5) The display device of claim 5, wherein the first input portion includes a first input transistor, and wherein the first input transistor includes a gate electrode to which the first clock signal is applied, a source electrode to which the input signal is applied, and a drain electrode connected to the first node. ### Claim 14 (depends on 5) The display device of claim 5, wherein an (N)th stage represents a selected stage among the stages, wherein the first output portion includes a first output transistor and a first capacitor, wherein the first output transistor includes a gate electrode connected to the first node, a source electrode to which the second clock signal is applied, and a drain electrode connected to an output terminal that is configured to output the (N)th gate output signal, and wherein the first capacitor includes a first electrode connected to the first node and a second electrode connected to the output terminal. ### Claim 15 (depends on 5) The display device of claim 5, wherein the second input portion includes a second input transistor, and wherein the second input transistor includes a gate electrode connected to the first node, a source electrode to which the first clock signal is applied, and a drain electrode connected to the second node. ### Claim 16 (depends on 5) The display device of claim 5, wherein the second output portion includes a second output transistor and a second capacitor, wherein the second output transistor includes a gate electrode connected to the second node, a source electrode to which the first voltage is applied, and a drain electrode connected to an output terminal that outputs the (N)th gate output signal, and wherein the second capacitor includes a first electrode connected to the second node and a second electrode to which the first voltage is applied. ### Claim 17 (depends on 5) The display device of claim 5, wherein the output control portion includes an output control transistor, and wherein the output control transistor includes a gate electrode to which the output control signal is applied, a source electrode to which a second voltage is applied, and a drain electrode connected to the first node.