# US 9,436,972 B2 · System coherency in a distributed graphics processor hierarchy > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,972 B2 - Document ID: US9436972B2 - Status: Granted - Kind: B2 - Application number: 14/227,525 - Filed: 2014-03-27 - Published: 2015-10-01 - Granted: 2016-09-06 - Earliest claimed: 2014-03-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Altug Koker; Aditya Navale - Web page: https://patentgrep.com/patent/US9436972B2 ## CPC - G06T 1/60: Memory management - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0813: with a network or matrix configuration - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 2212/1024: Latency reduction - G06F 2212/455: Image or video data - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice. ## Claims ### Claim 1 A system comprising: a display to present visual content; a system cache coupled to one or more host processors and a system memory; a graphics interface coupled to the system cache; and a graphics processor coupled to the graphics interface, the graphics processor including: a physically distributed set of compute slices to execute a plurality of work items associated with the visual content, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units, and a cache fabric to maintain a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, the system memory and the one or more host processors, wherein the cache fabric includes, a plurality of level one (L1) caches, each L1 cache being dedicated to an execution block of a compute slice, a physically distributed shared cache structure, wherein the coherency of the one or more memory lines is to be maintained across the plurality of L1 caches and the shared cache structure across the physically distributed set of compute slices, wherein the shared cache structure includes a level two (L2) cache having a plurality of banks, and wherein the shared cache structure is to hash at least one of the one or more memory lines across the plurality of banks, and a plurality of crossbar nodes to track the one or more memory lines, each crossbar node being dedicated to a compute slice and each crossbar node of the plurality of crossbar nodes being connected to the L1 cache of each of the plurality of execution blocks of the compute slice to which the crossbar node is dedicated, the plurality of crossbar nodes further to distribute one or more snoop requests originating from the system cache to the shared cache structure and the plurality of L1 caches via the graphics interface, collect one or more snoop results from the shared cache structure and the plurality of L1 caches, and communicate the one or more snoop results to the system cache. ### Claim 2 (depends on 1) The system of claim 1, wherein the shared cache structure includes a plurality of independent level two (L2) caches, each L2 cache being dedicated to a compute slice. ### Claim 3 (depends on 1) The system of claim 1, wherein the cache fabric is to use a modified, exclusive, shared, invalid (MESI) protocol to maintain the coherency of the one or more memory lines. ### Claim 4 A graphics processor comprising: a physically distributed set of compute slices to execute a plurality of work items, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units; and a cache fabric to maintain a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors, wherein the cache fabric includes: a plurality of level one (L1) caches, each L1 cache being dedicated to an execution block of a compute slice, wherein each compute slice has a plurality of execution blocks; a physically distributed shared cache structure, wherein the coherency of the one or more memory lines is to be maintained across the plurality of L1 caches and the shared cache structure across the physically distributed set of compute slices, wherein the shared cache structure includes a level two (L2) cache having a plurality of banks, and wherein the shared cache structure is to hash at least one of the one or more memory lines across the plurality of banks; and a plurality of crossbar nodes to track the one or more memory lines, each crossbar node being dedicated to a compute slice and each crossbar node of the plurality of crossbar nodes being connected to the L1 cache of each of the plurality of execution blocks of the compute slice to which the crossbar node is dedicated. ### Claim 5 (depends on 4) The graphics processor of claim 4, wherein the shared cache structure includes a plurality of independent level two (L2) caches, each L2 cache being dedicated to a compute slice. ### Claim 6 (depends on 4) The graphics processor of claim 4, wherein the plurality of crossbar nodes are to distribute one or more snoop requests originating from a system cache coupled to the one or more host processors to the shared cache structure and the plurality of L1 caches. ### Claim 7 (depends on 6) The graphics processor of claim 6, wherein the plurality of crossbar nodes are to collect one or more snoop results from the shared cache structure and the plurality of L1 caches, and communicate the one or more snoop results to a system cache coupled to the one or more host processors. ### Claim 8 (depends on 4) The graphics processor of claim 4, wherein the cache fabric is to use a modified, exclusive, shared, invalid (MESI) protocol to maintain the coherency of the one or more memory lines. ### Claim 9 A system comprising: a display to present visual content; and a graphics processor including: a physically distributed set of compute slices to execute a plurality of work items associated with the visual content, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units, and a cache fabric to maintain a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors, wherein the cache fabric includes: a plurality of level one (L1) caches, each L1 cache being dedicated to an execution block of a compute slice, wherein each compute slice has a plurality of execution blocks; a physically distributed shared cache structure, wherein the coherency of the one or more memory lines is to be maintained across the plurality of L1 caches and the shared cache structure across the physically distributed set of compute slices, wherein the shared cache structure includes a level two (L2) cache having a plurality of banks, and wherein the shared cache structure is to hash at least one of the one or more memory lines across the plurality of banks; and a plurality of crossbar nodes to track the one or more memory lines, each crossbar node being dedicated to a compute slice and each crossbar node of the plurality of crossbar nodes being connected to the L1 cache of each of the plurality of execution blocks of the compute slice to which the crossbar node is dedicated. ### Claim 10 (depends on 9) The system of claim 9, wherein the shared cache structure includes a plurality of independent level two (L2) caches, each L2 cache being dedicated to a compute slice. ### Claim 11 (depends on 9) The system of claim 9, wherein the plurality of crossbar nodes are to distribute one or more snoop requests originating from a system cache coupled to the one or more host processors to the shared cache structure and the plurality of L1 caches. ### Claim 12 (depends on 11) The system of claim 11, further including a system cache coupled to the one or more host processors and the system memory, and a graphics interface coupled to the system cache, wherein the plurality of crossbar nodes are to collect one or more snoop results from the shared cache structure and the plurality of L1 caches, and communicate the one or more snoop results to the system cache via the graphics interface. ### Claim 13 (depends on 9) The system of claim 9, wherein the cache fabric is to use a modified, exclusive, shared, invalid (MESI) protocol to maintain the coherency of the one or more memory lines. ### Claim 14 A method of operating a graphics processor, comprising: executing, by a physically distributed set of compute slices, a plurality of work items, wherein each compute slice includes a plurality of execution blocks each having a plurality of execution units; maintaining, by a cache fabric, a coherency of one or more memory lines associated with the plurality of work items across the graphics processor, a system memory and one or more host processors; hashing at least one of the one or more memory lines across a plurality of banks of a level two (L2) cache; and tracking, by a plurality of crossbar nodes, the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure across the physically distributed set of compute slices, each L1 cache being dedicated to an execution block of a compute slice and each crossbar node being dedicated to a compute slice having a plurality of execution blocks and being connected to the L1 cache of each of the plurality of execution blocks. ### Claim 15 (depends on 14) The method of claim 14, wherein the shared cache structure uses a plurality of independent level two (L2) caches to track the one or more memory lines, each L2 cache being dedicated to a compute slice. ### Claim 16 (depends on 14) The method of claim 14, further including distributing, by the plurality of crossbar nodes, one or more snoop requests originating from a system cache coupled to the one or more host processors to the shared cache structure and the plurality of L1 caches. ### Claim 17 (depends on 16) The method of claim 16, further including: collecting, by the plurality of crossbar nodes, one or more snoop results from the shared cache structure and the plurality of L1 caches; and communicating, by the plurality of crossbar nodes, the one or more snoop results to a system cache coupled to the one or more host processors. ### Claim 18 (depends on 14) The method of claim 14, further including using, by the cache fabric, a modified, exclusive, shared, invalid (MESI) protocol to maintain the coherency of the one or more memory lines.