# US 9,436,845 B2 · Physically unclonable fuse using a NOR type memory array

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- Number: US 9,436,845 B2
- Document ID: US9436845B2
- Status: Granted
- Kind: B2
- Application number: 14/224,099
- Filed: 2014-03-25
- Published: 2015-10-01
- Granted: 2016-09-06
- Earliest claimed: 2014-03-25
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries U.S. 2 LLC
- Inventors: Subramanian S. Iyer; Toshiaki Kirihata; Chandrasekharan Kothandaraman; Derek H. Leu; Sami Rosenblatt
- Web page: https://patentgrep.com/patent/US9436845B2

## CPC

- G06F 21/70: Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F 21/44: Program or device authentication
- G06F 21/73: by creating or determining hardware identification, e.g. serial numbers
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/20: Initialising; Data preset; Chip identification
- G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells
- G11C 16/24: Bit-line control circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G06F 2221/2103: Challenge-response
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 9/3278: {using physically unclonable functions [PUF]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.

## Claims

### Claim 1

A method for providing an unclonable identifying chip comprising:
forming a memory array consisting of memory cells arranged in a matrix, each of the memory cells having one NMOS transistor, wherein the NMOS transistors in each row are coupled to a wordline, and the NMOS transistors in each column are coupled to a bitline and to a source line, the source line having a voltage (VDD);
activating the wordline and forcing the bitline to a predetermined voltage, the predetermined voltage being lower than the voltage VDD,
wherein a threshold voltage of the NMOS transistor of the memory cell is increased by providing the NMOS transistor with a charge trapping in response to applying an elevated wordline voltage to the activated wordline, and providing a voltage higher than the voltage VDD to the source line and forcing a corresponding bitline to ground (GND) during the activation of the wordline;
floating the bitline followed by precharging the bitline through the NMOS transistor coupled to the activated wordline; and
sensing the bitline voltage, wherein random binary strings are generated by sensing results of the bitline voltage.

### Claim 2 (depends on 1)

The method of claim 1, wherein said sensing is realized by comparing said bitline voltage with a predetermined reference voltage.

### Claim 3 (depends on 2)

The method of claim 2, wherein said predetermined reference voltage is provided by said transistor of said memory cell, and having said NMOS gate and drain coupled to said VDD, and said source of said NMOS is first lowered and subsequently floated.

### Claim 4

A method providing an unclonable identifying chip comprising:
forming a memory array, consisting of memory cells arranged in a matrix, each memory cell having two NMOS transistors, wherein a gate of the NMOS transistors in each row is coupled to a wordline, and a source of a first one of the two NMOS transistors in each column is coupled to a true bitline, and a source of a second one of the two NMOS transistors in each column is coupled to a complement bitline, and a drain of the two NMOS transistors is coupled to a source line having a voltage (VDD);
activating the wordline, and forcing a voltage to the true and the complement bitlines to a predetermined voltage, the predetermined voltage being lower than the voltage VDD,
wherein a threshold voltage of at least one of the NMOS transistors of the memory cell is increased by providing the at least one of the NMOS transistors with a charge trapping in response to applying an elevated wordline voltage to the activated wordline, and providing a voltage higher than the voltage VDD to the source line and forcing a corresponding bitline to ground (GND) during the activation of the wordline;
floating the true and the complement bitlines;
precharging the bitline through the NMOS transistor coupled to the activated wordline; and
sensing a differential voltage of the true and the complement bitlines,
wherein random binary strings are generated by sensing results of the differential bitline voltage.

### Claim 5 (depends on 4)

The method of claim 4, wherein said random binary string are generated by said memory cell with two of non-trapped of said NMOS transistors.

### Claim 6 (depends on 5)

The method of claim 5, wherein a subset of said memory cells is provided with error-correction-code (ECC) bits for correcting a generated PUF using an ECC logic circuit.

### Claim 7 (depends on 6)

The method of claim 6, wherein said error correction bits are programmed by said trapped charge.