# US 9,436,833 B2 · Security circuits and security systems including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,833 B2 - Document ID: US9436833B2 - Status: Granted - Kind: B2 - Application number: 14/499,724 - Filed: 2014-09-29 - Published: 2015-06-11 - Granted: 2016-09-06 - Earliest claimed: 2013-12-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ji-Myung Na; Kee-Moon Chun - Web page: https://patentgrep.com/patent/US9436833B2 ## CPC - G06F 21/60: Protecting data - G06F 21/71: to assure secure computing or processing of information - G06F 21/84: output devices, e.g. displays or monitors - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal. ## Claims ### Claim 1 A security circuit, comprising: a functional circuit including a test chain that connects a plurality of flip-flops to check a circuit modification of the functional circuit according to a circuit modification check command, the functional circuit configured to generate a test data output signal based on a test control signal, a hardware test mode signal, and the test chain; and a hardware test controller configured to generate the test data input signal, the test control signal, and the hardware test mode signal, and configured to generate an authentication result based on the test data output signal. ### Claim 2 (depends on 1) The security circuit of claim 1, wherein the hardware test controller comprises: a signal generator configured to generate the test data input signal based on an authentication data signal; a data storage unit configured to store an expected test data output signal corresponding to the test data input signal; and a comparator configured to generate the authentication result by comparing the test data output signal and the expected test data output signal. ### Claim 3 (depends on 2) The security circuit of claim 2, wherein the signal generator is further configured to generate the test control signal and the hardware test mode signal based on a test start signal, which is generated periodically by the signal generator, or an authentication command signal. ### Claim 4 (depends on 2) The security circuit of claim 2, wherein the data storage unit is further configured to store the authentication data signal, and wherein the data storage unit is further configured to provide the authentication data signal to the signal generator. ### Claim 5 (depends on 1) The security circuit of claim 1, wherein the functional circuit further comprises: a plurality of combinational logic circuits configured to perform an executing function based on stored values of the flip-flops and combinational logic circuit input signals. ### Claim 6 (depends on 5) The security circuit of claim 5, wherein the hardware test controller is further configured to generate the combinational logic circuit input signals based on an authentication data signal. ### Claim 7 (depends on 6) The security circuit of claim 6, wherein the functional circuit is further configured to generate the test data output signal by encrypting the test data input signal based on the combinational logic circuit input signals. ### Claim 8 (depends on 1) The security circuit of claim 1, wherein the hardware test controller is further configured to disable the security circuit or to operate the security circuit in a protection mode when the authentication result represents a failure of authentication. ### Claim 9 (depends on 1) The security circuit of claim 1, wherein the hardware test controller is further configured to enable the hardware test mode signal during a reset time or a run time of the functional circuit. ### Claim 10 A security system, comprising: a first controller configured to generate an authentication command signal and an authentication data signal; and a security product including a security circuit which includes: a functional circuit including a test chain that connects a plurality of flip-flops to check genuineness of the functional circuit according to a genuineness check command signal, the functional circuit configured to generate a test data output signal by encrypting a test data input signal based on a test control signal, a hardware test mode signal, and the test chain; and a hardware test controller configured to generate the test control signal and the hardware test mode signal based on the authentication command signal, and configured to generate the test data input signal based on the authentication data signal. ### Claim 11 (depends on 10) The security system of claim 10, wherein the first controller comprises: a data storage unit configured to store an expected test data output signal corresponding to the test data input signal; and a comparator configured to generate an authentication result by comparing the test data output signal and the expected test data output signal. ### Claim 12 (depends on 11) The security system of claim 11, wherein the first controller is further configured to disable the security product when the authentication result represents a failure of authentication. ### Claim 13 (depends on 11) The security system of claim 11, wherein the first controller is further configured to disable the security circuit or to operate the security circuit in a protection mode when the authentication result represents a failure of authentication. ### Claim 14 (depends on 10) The security system of claim 10, wherein the hardware test controller comprises: a signal generator configured to generate the test control signal and the hardware test mode signal based on the authentication command signal, and configured to generate the test data input signal based on the authentication data signal; a data storage unit configured to store an expected test data output signal corresponding to the test data input signal; and a comparator configured to generate an authentication result by comparing the test data output signal and the expected test data output signal. ### Claim 15 (depends on 14) The security system of claim 14, wherein the first controller is further configured to disable the security product when the authentication result provided from the hardware test controller represents a failure of authentication. ### Claim 16 (depends on 14) The security system of claim 14, wherein the first controller is further configured to disable the security circuit or to operate the security circuit in a protection mode when the authentication result represents a failure of authentication. ### Claim 17 A security circuit, comprising: a first device comprising a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second signal, the third signal, and the test chain; and a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal; wherein the second device is configured to enable a hardware test mode signal during a setup time or a run time of the first device. ### Claim 18 (depends on 17) The security circuit of claim 17, wherein the second device is further configured to disable the security circuit when the authentication result represents a failure of authentication. ### Claim 19 (depends on 17) The security circuit of claim 17, wherein the second device is further configured to operate the security circuit in a protection mode when the authentication result represents a failure of authentication. ### Claim 20 (depends on 17) The security circuit of claim 17, wherein the second device is further configured to disable the security circuit or to operate the security circuit in a protection mode when the authentication result represents a failure of authentication.