# US 9,436,793 B2 · Tier based layer promotion and demotion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,793 B2 - Document ID: US9436793B2 - Status: Granted - Kind: B2 - Application number: 14/166,974 - Filed: 2014-01-29 - Published: 2015-07-30 - Granted: 2016-09-06 - Earliest claimed: 2014-01-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Yen-Hung Lin; Chi Wei Hu; Yuan-Te Hou; Chung-Hsing Wang; Chin-Chou Liu - Web page: https://patentgrep.com/patent/US9436793B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified. ## Claims ### Claim 1 A method for tier based layer modification for a design layout, comprising: evaluating a metal scheme for a design layout to group metal layers of the design layout into a set of tiers based upon a resistivity associated with the respective metal layers; identifying a first net within the design layout, the first net comprising a first wire segment; determining a current performance for the first wire segment based upon a current tier, of the set of tiers, to which the first wire segment is assigned; determining a potential performance for the first wire segment based upon a potential tier, of the set of tiers, to which the first wire segment could be reassigned; evaluating the current performance and the potential performance to either retain an assignment of the first wire segment to the current tier or reassign the first wire segment to the potential tier; and forming the first wire segment within an integrated circuit according to the design layout, wherein: the first wire segment is formed within a metal layer of the current tier when the assignment of the first wire segment to the current tier is retained; and the first wire segment is formed within a metal layer of the potential tier when the first wire segment is reassigned to the potential tier. ### Claim 2 (depends on 1) The method of claim 1, the evaluating a metal scheme comprising: grouping a first metal layer and a second metal layer into a tier based upon the first metal layer having a first resistance property corresponding to a second resistance property of the second metal layer. ### Claim 3 (depends on 1) The method of claim 1, comprising: determining that the first wire segment comprises a timing relevant segment; and identifying the potential tier as a promotion tier with respect to the current tier based upon the timing relevant segment. ### Claim 4 (depends on 3) The method of claim 3, the promotion tier having a first resistance property that is smaller than a second resistance property of the current tier. ### Claim 5 (depends on 1) The method of claim 1, comprising: determining that the first wire segment comprises a non-timing relevant segment; and identifying the potential tier as a demotion tier with respect to the current tier based upon the non-timing relevant segment. ### Claim 6 (depends on 5) The method of claim 5, the demotion tier having a first resistance property that is larger than a second resistance property of the current tier. ### Claim 7 (depends on 1) The method of claim 1, comprising: responsive to retaining the assignment of the first wire segment to the current tier, modifying a size parameter of the first wire segment. ### Claim 8 (depends on 1) The method of claim 1, comprising: responsive to retaining the assignment of the first wire segment to the current tier, inserting a buffer into the current tier with respect to the first wire segment. ### Claim 9 (depends on 1) The method of claim 1, the determining a potential performance comprising: identifying a via count penalty associated with reassigning the first wire segment to the potential tier; and specifying the potential performance based upon the via count penalty. ### Claim 10 (depends on 1) The method of claim 1, the determining a potential performance comprising: identifying a routing resource gain associated with reassigning the first wire segment to the potential tier; and specifying the potential performance based upon the routing resource gain. ### Claim 11 A system for tier based layer promotion for a design layout, comprising: at least one of a promotion component or a demotion component configured to: evaluate a metal scheme for a design layout to group metal layers of the design layout into a set of tiers based upon a resistivity associated with the respective metal layers; identify a first net within the design layout, the first net comprising a first wire segment; determine a current performance for the first wire segment based upon a current tier to which the first wire segment is assigned; determine a potential performance for the first wire segment based upon a promotion tier to which the first wire segment could be reassigned; and evaluate the current performance and the potential performance to either retain an assignment of the first wire segment to the current tier or reassign the first wire segment to the promotion tier, wherein the first wire segment is formed within an integrated circuit according to the design layout, the first wire segment formed within a metal layer of the current tier when the assignment of the first wire segment to the current tier is retained; and the first wire segment formed within a metal layer of the promotion tier when the first wire segment is reassigned to the promotion tier. ### Claim 12 (depends on 11) The system of claim 11, the first wire segment comprising a timing relevant segment. ### Claim 13 (depends on 11) The system of claim 11, the promotion tier having a first resistance property that is smaller than a second resistance property of the current tier. ### Claim 14 (depends on 11) The system of claim 11, the promotion component configured to: identify a via count penalty associated with reassigning the first wire segment to the promotion tier; and specify the potential performance based upon the via count penalty. ### Claim 15 (depends on 11) The system of claim 11, the promotion component configured to: responsive to retaining the assignment of the first wire segment to the current tier, at least one of modify a size parameter of the first wire segment or insert a buffer into the current tier with respect to the first wire segment. ### Claim 16 A non-transitory computer readable medium comprising instructions that when executed perform operations, comprising: evaluating a metal scheme for a design layout to group metal layers of the design layout into a set of tiers; identifying a first net within the design layout, the first net comprising a first wire segment; determining a current performance for the first wire segment based upon a current tier to which the first wire segment is assigned; determining a potential performance for the first wire segment based upon a demotion tier to which the first wire segment could be reassigned, the determining comprising: identifying a routing resource gain associated with reassigning the first wire segment to the demotion tier; and specifying the potential performance based upon the routing resource gain; evaluating the current performance and the potential performance to either retain an assignment of the first wire segment to the current tier or reassign the first wire segment to the demotion tier; and forming the first wire segment within an integrated circuit according to the design layout, wherein: the first wire segment is formed within a metal layer of the current tier when the assignment of the first wire segment to the current tier is retained; and the first wire segment is formed within a metal layer of the demotion tier when the first wire segment is reassigned to the demotion tier. ### Claim 17 (depends on 16) The non-transitory computer readable medium of claim 16, the first wire segment comprising a non-timing relevant segment. ### Claim 18 (depends on 16) The non-transitory computer readable medium of claim 16, the demotion tier having a first resistance property that is larger than a second resistance property of the current tier. ### Claim 19 (depends on 16) The non-transitory computer readable medium of claim 16, the evaluating a metal scheme for a design layout comprising: grouping metal layers of the design layout into the set of tiers based upon a resistivity associated with the respective metal layers. ### Claim 20 (depends on 16) The non-transitory computer readable medium of claim 16, the operations comprising: responsive to retaining the assignment of the first wire segment to the current tier, at least one of modifying a size parameter of the first wire segment or inserting a buffer into the current tier with respect to the first wire segment.