# US 9,436,789 B2 · Structure, method and system for complementary strain fill for integrated circuit chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,789 B2 - Document ID: US9436789B2 - Status: Granted - Kind: B2 - Application number: 14/517,292 - Filed: 2014-10-17 - Published: 2015-02-05 - Granted: 2016-09-06 - Earliest claimed: 2011-01-03 - Assignees: Globalfoundries Inc. - Applicants: Globalfoundries Inc. - Inventors: Brent A. Anderson; Edward J. Nowak; Jed H. Rankin - Web page: https://patentgrep.com/patent/US9436789B2 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 30/792: {comprising applied insulating layers, e.g. stress liners} - H10D 84/0128: {Manufacturing their channels} - H10D 84/0167: {Manufacturing their channels} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 89/10: Integrated device layouts - H10D 84/0119: {the components including complementary BJTs} - H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D 86/01: Manufacture or treatment - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer. ## Claims ### Claim 1 A computer system comprising: a processor; and a computer-readable memory device coupled to communicate with said processor, said memory device containing instructions that, when executed by the processor, implement a method for complementary strain fill for integrated circuit chips by: generating an integrated circuit chip design for an integrated circuit chip; generating a tensile layer etch mask design for an etch mask used to etch a tensile stressed dielectric layer as specified in said integrated circuit chip design; generating a second mask design for an etch mask used to etch a compressive stressed dielectric layer as specified in said integrated circuit chip design; identifying active regions of an integrated circuit having a plurality of n-channel field effect transistors (NFETs) and a plurality of p-channel field effect transistors (PFETs); identifying inactive regions of said integrated circuit design not containing NFETs or PFETs; placing fill shapes in said layer etch mask design and in said compressive layer etch mask design, said fill shapes placed only in respective regions of said tensile layer etch mask design and said compressive layer etch mask design corresponding to said inactive regions, and said fill shapes defining areas of said tensile stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said tensile layer etch mask design and areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said compressive layer etch mask design; and storing said tensile and compressive etch mask designs on a computer readable device. ### Claim 2 (depends on 1) The computer system of claim 1, further comprising: identifying sub-regions of said active regions, said sub-regions not containing FETs; and placing additional fill shapes in said tensile and compressive layer etch mask designs, said additional fill shapes placed only in regions of said tensile and compressive layer etch mask designs corresponding to said sub-regions such that when PFETs are the predominate type of FET in said active regions a tensile layer will result on said integrated circuit chip fabricated from said tensile and compressive layer etch mask designs and when NFETs are the predominate FETs of said sub-regions a tensile layer will result on said integrated circuit chip fabricated from said tensile and compressive layer etch mask designs. ### Claim 3 (depends on 1) The computer system of claim 1, further comprising: placing first additional fill shapes in said tensile layer etch mask design, said additional fill shapes placed only in regions of said tensile layer etch mask design where NFETs predominate; and placing second additional fill shapes in said compressive layer etch mask design, said additional fill shapes placed only in regions of said compressive layer etch mask design where PFETs predominate. ### Claim 4 (depends on 1) The computer system of claim 1, wherein greater than 70% of the area of each active region of said integrated circuit design contains NFETs, PFETS, or both. ### Claim 5 (depends on 1) The computer system of claim 1, wherein said fill shapes are placed in said tensile layer etch mask design corresponding to said inactive regions only when greater than 70% of the area of said corresponding active regions of said integrated circuit design contains NFETs. ### Claim 6 (depends on 1) The computer system of claim 1, wherein said fill shapes are placed in said compressive layer etch mask design corresponding to said inactive regions only when greater than 70% of the area of said corresponding active regions of said integrated circuit design contains PFETs. ### Claim 7 (depends on 1) The computer system of claim 1, wherein said tensile layer etch mask design and said compressive layer etch mask design are stored in a netlist. ### Claim 8 (depends on 1) The computer system of claim 1, wherein said tensile layer etch mask design and said compressive layer etch mask design are stored in a shapes file. ### Claim 9 (depends on 1) The computer system of claim 1, wherein said computer readable storage device is selected from the group consisting of magnetic tape, a removable computer diskette, a random access memory device, a read only memory device, a rigid magnetic disk and an optical disk. ### Claim 10 (depends on 1) The computer system of claim 1, wherein said fill shapes comprise material from the compressive stressed dielectric layer added to the areas of said tensile stressed dielectric layer that are removed from said integrated circuit chip fabricated using said tensile layer etch mask design and material from the tensile stressed dielectric layer added to the areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated using said compressive layer etch mask design. ### Claim 11 A computer system comprising: a processor; and a computer-readable memory device coupled to communicate with said processor, said memory device containing instructions that, when executed by the processor, implement a method for complementary strain fill for integrated circuit chips by: generating an integrated circuit chip design for an integrated circuit chip; generating a tensile layer etch mask design for an etch mask used to etch a tensile stressed dielectric layer as specified in said integrated circuit chip design; generating a second mask design for an etch mask used to etch a compressive stressed dielectric layer as specified in said integrated circuit chip design; identifying active regions of an integrated circuit having a plurality of field effect transistors (FETs) distributed among a plurality of n-channel field effect transistors (nFETs) and a plurality of p-channel field effect transistors (pFETs); identifying low field effect transistor (FET) density regions of said integrated circuit design, said low FET density regions containing less than 10% FETs by area; placing fill shapes in said layer etch mask design and in said compressive layer etch mask design, said fill shapes placed only in respective regions of said tensile layer etch mask design and said compressive layer etch mask design corresponding to said low FET density regions, and said fill shapes defining areas of said tensile stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said tensile layer etch mask design and areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated based on said compressive layer etch mask design; and storing said tensile and compressive etch mask designs on a computer readable device. ### Claim 12 (depends on 11) The computer system of claim 11, further comprising: identifying sub-regions of said active regions, said sub-regions not containing FETs; and placing additional fill shapes in said tensile and compressive layer etch mask designs, said additional fill shapes placed only in regions of said tensile and compressive layer etch mask designs corresponding to said sub-regions such that when PFETs are the predominate type of FET in said active regions a tensile layer will result on said integrated circuit chip fabricated from said tensile and compressive layer etch mask designs and when NFETs are the predominate FETs of said sub-regions a tensile layer will result on said integrated circuit chip fabricated from said tensile and compressive layer etch mask designs. ### Claim 13 (depends on 11) The computer system of claim 11, further comprising: placing first additional fill shapes in said tensile layer etch mask design, said additional fill shapes placed only in regions of said tensile layer etch mask design where NFETs predominate; and placing second additional fill shapes in said compressive layer etch mask design, said additional fill shapes placed only in regions of said compressive layer etch mask design where PFETs predominate. ### Claim 14 (depends on 11) The computer system of claim 11, wherein greater than 70% of the area of each active region of said integrated circuit design contains FETs. ### Claim 15 (depends on 11) The computer system of claim 11, wherein said fill shapes are placed in said tensile layer etch mask design corresponding to said low FET density regions only when greater than 70% of the area of said corresponding active regions of said integrated circuit design contains NFETs. ### Claim 16 (depends on 11) The computer system of claim 11, wherein said fill shapes are placed in said compressive layer etch mask design corresponding to said low FET density regions only when greater than 70% of the area of said corresponding active regions of said integrated circuit design contains PFETs. ### Claim 17 (depends on 11) The computer system of claim 11, wherein said tensile layer etch mask design and said compressive layer etch mask design are stored in a netlist. ### Claim 18 (depends on 11) The computer system of claim 11, wherein said tensile layer etch mask design and said compressive layer etch mask design are stored in a shapes file. ### Claim 19 (depends on 11) The computer system of claim 11, wherein said computer readable storage device is selected from the group consisting of magnetic tape, a removable computer diskette, a random access memory device, a read only memory device, a rigid magnetic disk and an optical disk. ### Claim 20 (depends on 11) The computer system of claim 11, wherein said fill shapes comprise material from the compressive stressed dielectric layer added to the areas of said tensile stressed dielectric layer that are removed from said integrated circuit chip fabricated using said tensile layer etch mask design and material from the tensile stressed dielectric layer added to the areas of said compressive stressed dielectric layer to be removed from said integrated circuit chip fabricated using said compressive layer etch mask design.