# US 9,436,788 B2 · Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity

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- Number: US 9,436,788 B2
- Document ID: US9436788B2
- Status: Granted
- Kind: B2
- Application number: 14/253,282
- Filed: 2014-04-15
- Published: 2015-10-15
- Granted: 2016-09-06
- Earliest claimed: 2014-04-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jyuh-Fuh Lin; Pei-Yi Liu; Cheng-Hung Chen; Wen-Chuan Wang; Shy-Jay Lin; Burn Jeng Lin
- Web page: https://patentgrep.com/patent/US9436788B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10D 89/10: Integrated device layouts
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

## Claims

### Claim 1

An integrated circuit (IC) method comprising:
receiving an IC design layout including a plurality of main features;
choosing isolation distances to the IC design layout;
oversizing the main features according to the isolation distances;
generating a space block layer for the isolation distances by a Boolean operation, according to the oversized main features;
choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout, wherein the choosing of the optimized space block layer and the optimized block dummy density ratio includes choosing the optimized space block layer and the optimized block dummy density ratio according to the LVBDDR, wherein the calculating of the LVBDDR includes determining the LVBDDR r0 by a formula
r0=(PD0·PDs−PD0·PDs)/σs2,
where
PD0, is an average of the main pattern density;
PDs is an average of the dummy pattern density; and
σs is a standard deviation defined by
σs2=PDs2−(PDs)2;
and
generating dummy features in the optimized space block layer according to the optimized block dummy density ratio.

### Claim 2 (depends on 1)

The IC method of claim 1, wherein the oversizing the main features includes expanding edges of the main features by one of the isolation distances.

### Claim 3 (depends on 1)

The IC method of claim 1, wherein the oversizing the main features includes coalescing a subset of main features into one oversized main feature.

### Claim 4 (depends on 1)

The IC method of claim 1, wherein the generating of the space block layer includes defining the space block layer in regions of the IC design layout other than the oversized main features.

### Claim 5 (depends on 1)

The IC method of claim 1, wherein the choosing of the optimized space block layer and the optimized block dummy density ratio includes choosing the optimized space block layer and the optimized block dummy density ratio according to the LVBDDR and further according to process window and throughput.

### Claim 6 (depends on 1)

The IC method of claim 1, further comprising forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication, and wherein the forming of the tape-out data of the IC design layout includes forming the tape-out data of the IC design layout for mask making.

### Claim 7 (depends on 1)

The IC method of claim 1, further comprising forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication, and wherein the tape-out data is used to directly write the main features to an e-beam sensitive resist layer coated on a semiconductor substrate by an e-beam lithography exposing process.

### Claim 8 (depends on 1)

The IC method of claim 1, forming a tape-out data of the IC design layout including the main features and the dummy features.

### Claim 9

An integrated circuit (IC) method comprising:
receiving an IC design layout designed to have a plurality of main features to be formed on a semiconductor substrate;
choosing isolation distances to the IC design layout;
oversizing the main features according to the isolations distances;
generating space block layers by a Boolean operation to the IC design layout, wherein each of the space block layers is associated with one of the isolation distances;
dividing the semiconductor substrate into a plurality of templates;
calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout to the plurality of templates for each of the space block layers;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for the each of the space block layers according to the main pattern density and the dummy pattern density;
choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR;
generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and
forming a tape-out data of the modified IC design layout for IC fabrication,
wherein the calculating of the LVBDDR includes determining the LVBDDR r0 by a formula
r0=(PD0·PDs−PD0·PDs)/σs2,
where
PD0 is an average of the main pattern density;
PDs is an average of the dummy pattern density; and
σs is defined by a formula
σs2=PDs2−(PDs)2.

### Claim 10 (depends on 9)

The IC method of claim 9, wherein σ is defined by a formula
σ2=PD2−(PD)2,
where
PD is a total pattern density defined in a formula
PD=PD0+rPDs and
r is a block dummy density ratio.

### Claim 11 (depends on 9)

The IC method of claim 9, wherein the generating of the space block layer includes generating space blocks in the IC design layout for each of the space block layers according to a corresponding one of the isolation distances.

### Claim 12 (depends on 11)

The IC method of claim 11, wherein
the generating of the modified IC design layout includes generating dummy features in space blocks of the optimized space block layer; and
the dummy features has a local dummy pattern density determined by the optimized block dummy density ratio.

### Claim 13 (depends on 12)

The IC method of claim 12, wherein the generating of the dummy features in the space blocks of the optimized space block layer includes generating the dummy features of squares with size “a” and configured in an array with a pitch “p” such that a ratio a2/p2 is equal to the optimized block dummy density ratio.

### Claim 14 (depends on 12)

The IC method of claim 12, wherein the generating of the dummy features in the space blocks of the optimized space block layer includes generating the dummy features of rectangles that spans a first dimension “a” in a first direction and a second dimension “b” in a second direction orthogonal to the first direction, wherein the dummy features are configure in an array with a first pitch “px” in the first direction and a second pitch “py” in the second direction such that a ratio ab/pxpy is equal to the optimized block dummy density ratio.

### Claim 15 (depends on 9)

The IC method of claim 9, wherein the isolation distances are greater than or equal to a minimum isolation distance determined by at least one of defect-free process window and design rule.

### Claim 16

An integrated circuit (IC) method comprising:
receiving an IC design layout having a plurality of main features to be formed on a semiconductor substrate;
choosing isolation distances to the IC design layout;
oversizing the main features according to the isolations distances;
generating space block layers by a Boolean operation to the IC design layout, wherein each of the space block layers is associated with one of the isolation distances;
choosing an optimized space block layer and an optimized block dummy density ratio according to a least variation block dummy density ratio (LVBDDR) and process window; and
generating dummy features in the optimized space block layer according to the optimized block dummy density ratio, and
wherein the LVBDDR r0 is determined by a formula
r0=(PD0·PDs−PD0·PDs)/σs2,
where
PD0 is a main pattern density;
PDs is a dummy pattern density; and
σs is defined by a formula
σs2=PDs2−(PDs)2.

### Claim 17 (depends on 16)

The IC method of claim 16, wherein the generating of the dummy features in the space blocks includes generating the dummy features of squares with size “a” and configured in an array with a pitch “p” such that a ratio a2/p2 is equal to the optimized block dummy density ratio.

### Claim 18 (depends on 16)

The IC method of claim 16, wherein the generating of the dummy features in the space blocks includes generating the dummy features of rectangles that spans a first dimension “a” in a first direction and a second dimension “b” in a second direction orthogonal to the first direction, wherein the dummy features are configured in an array with a first pitch “px” in the first direction and a second pitch “py” in the second direction such that a ratio ab/pxpy is equal to the optimized block dummy density ratio.

### Claim 19 (depends on 16)

The IC method of claim 16, further comprising forming a tape-out data of the IC design layout including the main features and the dummy features.