# US 9,436,787 B2 · Method of fabricating an integrated circuit with optimized pattern density uniformity

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- Number: US 9,436,787 B2
- Document ID: US9436787B2
- Status: Granted
- Kind: B2
- Application number: 14/252,464
- Filed: 2014-04-14
- Published: 2015-10-15
- Granted: 2016-09-06
- Earliest claimed: 2014-04-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jyuh-Fuh Lin; Pei-Yi Liu; Cheng-Hung Chen; Wen-Chuan Wang; Shy-Jay Lin; Burn Jeng Lin
- Web page: https://patentgrep.com/patent/US9436787B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10D 89/10: Integrated device layouts
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.

## Claims

### Claim 1

An integrated circuit (IC) method comprising:
receiving an IC design layout having main features;
generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks, wherein the isolation distance is greater than or equal to a minimum isolation distance determined by a process window;
calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density;
choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR;
generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and
forming a tape-out data of the modified IC design layout for IC fabrication.

### Claim 2 (depends on 1)

The IC method of claim 1, wherein calculating the LVBDDR includes determining the LVBDDR r0 by a formula r0=(PD0·PDs−PD0·PDs)/σs2, where
PD0 is an average of the main pattern density;
PDs is an average of the dummy pattern density;
PD0·PDs is an average of a product of the main pattern density and the dummy pattern density; and
σs is a standard deviation defined by a formula σs2=PDs2−(PDs)2.

### Claim 3 (depends on 1)

The IC method of claim 1, wherein choosing the optimized space block layer and the optimized block dummy density ratio includes choosing the optimized space block layer and the optimized block dummy density ratio according to the LVBDDR and further according to a pattern density uniformity and the process window.

### Claim 4 (depends on 1)

The IC method of claim 1, further comprising dividing a semiconductor substrate into a plurality of IC regions, wherein calculating the main pattern density PD0 and the dummy pattern density PDS includes calculating the main pattern density PD0 and the dummy pattern density PDs for each of the plurality of IC regions.

### Claim 5 (depends on 1)

The IC method of claim 1, wherein generating the plurality of space block layers includes generating space blocks in the IC design layout for each of the plurality of space block layers according to a corresponding isolation distance.

### Claim 6 (depends on 5)

The IC method of claim 5, wherein generating the modified IC design layout includes generating dummy features in the space blocks.

### Claim 7 (depends on 6)

The IC method of claim 6, wherein forming the tape-out data of the modified IC design layout includes forming the tape-out data of the modified IC design layout having main features and the dummy features for mask making.

### Claim 8 (depends on 5)

The IC method of claim 5, wherein forming the tape-out data of the modified IC design layout includes forming the tape-out data of the modified IC design layout, wherein the tape-out data is used to directly write the main features to an e-beam sensitive resist layer coated on a semiconductor substrate.

### Claim 9 (depends on 1)

The IC method of claim 1, further comprising writing the main features and the space blocks to an e-beam sensitive resist layer by an electron-beam exposure process.

### Claim 10

An integrated circuit (IC) method comprising:
receiving an IC design layout designed to have a plurality of main features to be formed on a semiconductor substrate;
generating a plurality of space block layers to the IC design layout according to various isolation distances, respectively, wherein the various isolation distances are greater than or equal to a minimum isolation distance determined by a process window;
dividing the semiconductor substrate into a plurality of templates;
calculating main pattern density PD0 of the IC design layout to the plurality of templates;
calculating dummy pattern density PDs to the plurality of templates for each of the space block layers;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for the each of the space block layers according to the main pattern density and the dummy pattern density;
choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR;
generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and
forming a tape-out data of the modified IC design layout for IC fabrication.

### Claim 11 (depends on 10)

The IC method of claim 10, wherein calculating the LVBDDR includes determining the LVBDDR r0 by a formula r0=(PD0·PDs−PD0·PDs)/σs2, where
PD0 is an average of the main pattern density over the IC templates;
PDs is an average of the dummy pattern density;
PD0·PDs is an average of a product of the main pattern density and the dummy pattern density; and
σs is defined by a formula σs2=PDs2−(PDs)2.

### Claim 12 (depends on 10)

The IC method of claim 10, wherein choosing the optimized space block layer and the optimized block dummy density ratio includes choosing the optimized space block layer and the optimized block dummy density ratio according to the LVBDDR and further according to a pattern density uniformity and the process window.

### Claim 13 (depends on 10)

The IC method of claim 10, wherein generating the space block layers includes generating space blocks in the IC design layout for each of the space block layers according to a corresponding one of the isolation distances.

### Claim 14 (depends on 13)

The IC method of claim 13, wherein
generating the modified IC design layout includes generating dummy features in the space blocks; and
the dummy features have a local dummy pattern density determined by the optimized block dummy density ratio.

### Claim 15 (depends on 14)

The IC method of claim 14, wherein forming the tape-out data of the modified IC design layout includes forming the tape-out data of the modified IC design layout having the main features and the dummy features for mask making.

### Claim 16 (depends on 13)

The IC method of claim 13, wherein forming the tape-out data of the modified IC design layout includes forming the tape-out data of the modified IC design layout having main features and space blocks, wherein the tape-out data is used to directly write the main features and the space blocks to an e-beam sensitive resist layer coated on a semiconductor substrate by an electron-beam lithography exposure process.

### Claim 17

An integrated circuit (IC) method comprising:
receiving an IC design layout having a plurality of main features to be formed on a semiconductor substrate;
generating a plurality of space block layers to the IC design layout according to various isolation distances, each of the space layers defining space blocks for non-circuit regions;
defining a plurality of templates on the semiconductor substrate;
calculating main pattern density PD0 of the IC design layout to the plurality of templates;
calculating dummy pattern density PDs to the plurality of templates for the each of the space block layers;
calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for the each of the space block layers according to the main pattern density and the dummy pattern density;
choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and process window;
generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio, wherein the modified IC design layout includes dummy features defined in the space blocks;
forming a tape-out data of the modified IC design layout for IC fabrication; and
directly writing the main features and the space blocks to an e-beam sensitive resist layer coated on a semiconductor substrate by an electron-beam lithography exposure process.

### Claim 18 (depends on 17)

The IC method of claim 17, wherein calculating the LVBDDR includes determining the LVBDDR r0 by a formula r0=(PD0·PDs−PD0·PDs)/σs2, where
PD0 is an average of the main pattern density over the IC templates;
PDs is an average of the dummy pattern density;
PD0·PDs is an average of a product of the main pattern density and the dummy pattern density; and
σs is defined by a formula σs2=PDs2−(PDs)2.

### Claim 19 (depends on 17)

The IC method of claim 17, further comprising dividing a semiconductor substrate into a plurality of IC regions, wherein calculating the main pattern density PD0 and calculating the dummy pattern density PDs includes calculating the main pattern density PD0 and the dummy pattern density PDs for each of the IC regions.

### Claim 20 (depends on 17)

The IC method of claim 17, wherein the various isolation distances are greater than or equal to a minimum isolation distance determined by a process window.