# US 9,436,785 B1 · Hierarchical preset and rule based configuration of a system-on-chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,785 B1 - Document ID: US9436785B1 - Status: Granted - Kind: B1 - Application number: 14/491,656 - Filed: 2014-09-19 - Granted: 2016-09-06 - Earliest claimed: 2014-09-19 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Somdutt Javre; Pradeep Kumar Mishra; Siddharth Rele - Web page: https://patentgrep.com/patent/US9436785B1 ## CPC - G06F 30/30: Circuit design - G06F 2213/0038: System on Chip - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Hierarchical preset and rule base configuration of a system-on-chip (SOC) includes receiving a user input selecting a first circuit block of the SOC for enablement and determining, using a processor, a first top level preset according to the user input for the first circuit block. Selected intermediate presets are determined from a plurality of hierarchically ordered presets for the first circuit block. Low level presets are automatically determined for the first circuit block according to the selected intermediate presets for the first circuit block. The low level presets are output, e.g., by loading them into the SOC. ## Claims ### Claim 1 A method, comprising: receiving a user input selecting a first circuit block of a system-on-chip for enablement; determining, using a processor, a first top level preset according to the user input for the first circuit block; determining selected intermediate presets from a plurality of hierarchically ordered presets for the first circuit block; automatically determining low level presets for the first circuit block according to the selected intermediate presets for the first circuit block; and configuring the system-on-chip by loading control register values specified by the low level presets into a control register of a processor system of the system-on-chip. ### Claim 2 (depends on 1) The method of claim 1, further comprising: detecting a conflict between at least one selected intermediate preset for the first circuit block and at least one selected intermediate preset for a second circuit block indicating that the first circuit block and the second circuit block are not compatible. ### Claim 3 (depends on 2) The method of claim 2, wherein detecting the conflict comprises: determining that the at least one selected intermediate preset for the first circuit block utilizes a same hardware resource of the system-on-chip as the at least one selected intermediate preset for the second circuit block. ### Claim 4 (depends on 3) The method of claim 3, further comprising: providing a notification that the first circuit block is not compatible with the second circuit block. ### Claim 5 (depends on 1) The method of claim 1, wherein the configuring the system-on-chip comprises: including the control register values within a circuit design specified as a configuration bitstream provided to the system-on-chip. ### Claim 6 (depends on 1) The method of claim 1, wherein: the intermediate presets are associated with rules; and determining the selected intermediate presets comprises determining a child intermediate preset from a plurality of candidate child intermediate presets of a parent intermediate preset within the plurality of hierarchically ordered presets, according to execution of a rule associated with the parent intermediate preset. ### Claim 7 A system, comprising: a processor programmed to initiate executable operations comprising: receiving a user input selecting a first circuit block of a system-on-chip for enablement; determining a first top level preset according to the user input for the first circuit block; determining selected intermediate presets from a plurality of hierarchically ordered presets for the first circuit block; automatically determining low level presets for the first circuit block according to the selected intermediate presets for the first circuit block; and configuring the system-on-chip by loading control register values specified by the low level presets into a control register of a processor system of the system-on-chip. ### Claim 8 (depends on 7) The system of claim 7, wherein the processor is further programmed to initiate executable operations comprising: detecting a conflict between at least one selected intermediate preset for the first circuit block and at least one selected intermediate preset for a second circuit block indicating that the first circuit block and the second circuit block are not compatible. ### Claim 9 (depends on 8) The system of claim 8, wherein detecting the conflict comprises: determining that the at least one selected intermediate preset for the first circuit block utilizes a same hardware resource of the system-on-chip as the at least one selected intermediate preset for the second circuit block. ### Claim 10 (depends on 9) The system of claim 9, wherein the processor is further programmed to initiate executable operations comprising: providing a notification that the first circuit block is not compatible with the second circuit block. ### Claim 11 (depends on 7) The system of claim 7, wherein the configuring the system-on-chip comprises: including the control register values within a circuit design specified as a configuration bitstream provided to the system-on-chip. ### Claim 12 (depends on 7) The system of claim 7, wherein: the intermediate presets are associated with rules; and determining the selected intermediate presets comprises determining a child intermediate preset from a plurality of candidate child intermediate presets of a parent intermediate preset within the plurality of hierarchically ordered presets, according to execution of a rule associated with the parent intermediate preset. ### Claim 13 A non-transitory computer-readable storage medium having instructions stored thereon which, when executed by a processor, perform a method comprising: receiving a user input selecting a first circuit block of a system-on-chip for enablement; determining, using the processor, a first top level preset according to the user input for the first circuit block; determining selected intermediate presets from a plurality of hierarchically ordered presets for the first circuit block; automatically determining low level presets for the first circuit block according to the selected intermediate presets for the first circuit block; and configuring the system-on-chip by loading control register values specified by the low level presets into a control register of a processor system of the system-on-chip. ### Claim 14 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein the method further comprises: detecting a conflict between at least one selected intermediate preset for the first circuit block and at least one selected intermediate preset for a second circuit block indicating that the first circuit block and the second circuit block are not compatible. ### Claim 15 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein detecting the conflict comprises: determining that the at least one selected intermediate preset for the first circuit block utilizes a same hardware resource of the system-on-chip as the at least one selected intermediate preset for the second circuit block. ### Claim 16 (depends on 15) The non-transitory computer-readable storage medium of claim 15, wherein the method further comprises: providing a notification that the first circuit block is not compatible with the second circuit block. ### Claim 17 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein: the intermediate presets are associated with rules; and determining the selected intermediate presets comprises determining a child intermediate preset from a plurality of candidate child intermediate presets of a parent intermediate preset within the plurality of hierarchically ordered presets, according to execution of a rule associated with the parent intermediate preset.