# US 9,436,647 B2 · IIC bus start-stop detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,647 B2 - Document ID: US9436647B2 - Status: Granted - Kind: B2 - Application number: 14/026,375 - Filed: 2013-09-13 - Published: 2015-03-19 - Granted: 2016-09-06 - Earliest claimed: 2013-09-13 - Assignees: STMicroelectronics Asia Pacific Pte Ltd - Applicants: STMicroelectronics Asia Pacific Pte. Ltd. - Inventors: Nee Loong Wilson Low; Chaochao Zhang - Web page: https://patentgrep.com/patent/US9436647B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation - G06F 13/4291: {using a clocked protocol} - G06F 2213/0016: Inter-integrated circuit (I2C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A start/stop condition detection circuit is coupled to receive the SDA and SCL signals from an IIC Bus. The circuit generates a first signal in response to an edge of the SDA signal and generates an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal. The first and second signals are logically combined to generate an output signal. The particular directions of the edges of the SDA and SCL signals that the circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection. ## Claims ### Claim 1 A circuit, comprising: a first input configured to receive an SDA signal; a second input configured to receive an SCL signal; a first logic circuit configured to generate a first signal having a first logic state in response to a rising edge of the SCL signal; a second logic circuit configured to invert the first signal and generate a second signal having a second logic state in response to a falling edge of the SDA signal; and a third logic circuit operable responsive to the first logic state of the first signal and second logic state of the second signal to generate a start signal indicative of a start condition on a bus comprising the SDA and SCL signals. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first logic circuit is a first flip-flop circuit clocked by the SCL signal. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the second logic circuit is a second flip flop circuit clocked by an inversion of the SDA signal. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the second logic circuit further comprises a multiplexing circuit having a first input coupled to receive the inverted first signal and having a selection functionality controlled by the SCL signal. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the multiplexing circuit further comprises a second input coupled to receive the second signal. ### Claim 6 (depends on 3) The circuit of claim 3, wherein the second signal output from the second flip-flop is input to the first flip-flop. ### Claim 7 (depends on 1) The circuit of claim 1, further comprising a fourth logic circuit coupled to receive an enable signal and the start signal, said fourth logic circuit configured to pass the start signal in response to said enable signal. ### Claim 8 (depends on 7) The circuit of claim 7, further comprising an additional logic circuit configured to generate the enable signal in response to said SDA and SCL signals. ### Claim 9 (depends on 8) The circuit of claim 8, wherein the additional logic circuit comprises: a fifth logic circuit configured to generate a fifth signal having a first logic state in response to a falling edge of the SDA signal; a sixth logic circuit configured to invert the fifth signal and generate a sixth signal having a second logic state in response to a rising edge of the SDA signal; and a seventh logic circuit operable responsive to the fifth and sixths signals to generate said enable signal. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the fifth logic circuit is a fifth flip-flop circuit clocked by an inversion of the SDA signal. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the fifth logic circuit further comprises a fifth multiplexor having a first input coupled to receive the fifth signal and a second input coupled to receive the sixth signal and having a selection functionality controlled by the SCL signal. ### Claim 12 (depends on 10) The circuit of claim 10, wherein the sixth logic circuit is a sixth flip-flop circuit clocked by the SDA signal. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the sixth logic circuit further comprises a sixth multiplexor having a first input coupled to receive the sixth signal and a second input coupled to receive the inverted fifth signal and having a selection functionality controlled by the SCL signal. ### Claim 14 (depends on 1) The circuit of claim 1, further comprising a finite state machined coupled to receive the start signal and the SCL signal, the finite state machine configured to check the logic state of the start signal at the rising edge of the SCL signal. ### Claim 15 A circuit, comprising: a first input configured to receive an SDA signal; a second input configured to receive an SCL signal; a first logic circuit configured to generate a first signal having a first logic state in response to a falling edge of the SCL signal; a second logic circuit configured to invert the first signal and generate a second signal having a second logic state in response to a rising edge of the SDA signal; and a third logic circuit operable responsive to the first logic state of the first signal and second logic state of the second signal to generate a stop signal indicative of a stop condition on a bus comprising the SDA and SCL signals. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the first logic circuit is a first flip-flop circuit clocked by an inversion of the SCL signal. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the second logic circuit is a second flip flop circuit clocked by the SDA signal. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the second logic circuit further comprises a multiplexing circuit having a first input coupled to receive the inverted first signal and having a selection functionality controlled by the SCL signal. ### Claim 19 (depends on 18) The circuit of claim 18, wherein the multiplexing circuit further comprises a second input coupled to receive the second signal. ### Claim 20 (depends on 17) The circuit of claim 17, wherein the second signal output from the second flip-flop is input to the first flip-flop. ### Claim 21 (depends on 15) The circuit of claim 15, further comprising a finite state machined coupled to receive the stop signal and the SCL signal, the finite state machine configured to check the logic state of the stop signal at the falling edge of the SCL signal. ### Claim 22 A circuit, comprising: a first input configured to receive an SDA signal; a second input configured to receive an SCL signal; a first circuit configured to sense a rising edge of the SCL signal and generate a first signal; a second circuit configured to sense a falling edge of the SDA signal and pass an inversion of the first signal as a second signal; and a logic circuit configured to logically combine the first and second signals to generate a start condition signal for a bus comprising the SDA and SCL signals. ### Claim 23 (depends on 22) The circuit of claim 22, further comprising an enable circuit configured to enable passing of the start condition signal, said enable circuit comprising: a third circuit configured to sense a falling edge of the SDA signal and generate a third signal; a fourth circuit configured to sense a rising edge of the SDA signal and an inversion of the third signal as a fourth signal; and an additional logic circuit configured to logically combine the third and fourth signals to generate said enable signal. ### Claim 24 A circuit, comprising: a first input configured to receive an SDA signal; a second input configured to receive an SCL signal; a first circuit configured to sense a falling edge of the SCL signal and generate a first signal; a second circuit configured to sense a rising edge of the SDA signal and pass an inversion of the first signal as a second signal; and a logic circuit configured to logically combine the first and second signals to generate a stop condition signal for a bus comprising the SDA and SCL signals. ### Claim 25 A circuit, comprising: a first input configured to receive an SDA signal; a second input configured to receive an SCL signal; a start/stop condition detection circuit coupled to receive the SDA and SCL signals and configured to: generate a first signal in response to an edge of the SDA signal; generate an inversion of the first signal as a second signal in response to an opposite edge of the SCL signal; and logically combine the first and second signals to generate an output signal indicative of start/stop condition detection. ### Claim 26 (depends on 25) The circuit of claim 25, wherein the particular directions of the edges of the SDA and SCL signals that the start/stop condition detection circuit is response to determines whether the output signal is indicative of a start condition detection or a stop condition detection.