# US 9,436,640 B1 · Full bandwidth packet handling with server systems including offload processors

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- Number: US 9,436,640 B1
- Document ID: US9436640B1
- Status: Granted
- Kind: B1
- Application number: 13/931,910
- Filed: 2013-06-29
- Granted: 2016-09-06
- Earliest claimed: 2013-01-17
- Assignees: Xockets, Inc.
- Applicants: Xockets, Inc.
- Inventors: Parin Bhadrik Dalal; Stephen Paul Belair
- Web page: https://patentgrep.com/patent/US9436640B1

## CPC

- G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/461: {Saving or restoring of program or task context}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 12/0815: Cache consistency protocols
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/285: {Halt processor DMA (G06F13/30 takes precedence)}
- G06F 13/362: with centralised access control
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 15/161: {Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning (casings, cabinets, racks or drawers for data centers H05K5/00)}
- G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)}
- H04L 47/193: at the transport layer, e.g. TCP related
- H04L 47/2441: relying on flow classification, e.g. using integrated services [IntServ]
- H04L 47/56: implementing delay-aware scheduling
- H04L 47/624: {Altering the ordering of packets in an individual queue}
- H04L 47/6295: using multiple queues, one for each individual QoS, connection, flow or priority
- H04L 49/90: Buffering arrangements
- H04L 61/103: across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
- H04L 61/2592: using tunnelling or encapsulation
- H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46)
- H04L 67/1097: for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
- G06F 2212/1024: Latency reduction
- H04L 49/40: Constructional details, e.g. power supply, mechanical construction or backplane
- H04L 2101/686: using dual-stack hosts, e.g. in Internet protocol version 4 [IPv4]/Internet protocol version 6 [IPv6] networks
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A rack server system for a map/reduce data processing is disclosed. The method can include a plurality of servers arranged in a rack, and a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, wherein the second offload processor module is configured to execute reduce steps of on data provided from the first offload processor module.

## Claims

### Claim 1

A rack server system for a map/reduce data processing, comprising:
a plurality of servers arranged in a rack, and
a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, wherein
a second offload processor module is configured to execute reduce steps of the map/reduce data processing on data provided from the first offload processor module, and
the first offload processor module is configured to generate virtual interrupts corresponding to the execution of the map steps.

### Claim 2 (depends on 1)

The system of claim 1 wherein each offload processor module is connected to a memory bus.

### Claim 3 (depends on 1)

The system of claim 1 wherein each offload processor module is connected to a memory bus on a server.

### Claim 4 (depends on 1)

The system of claim 1 wherein each offload processor module is physically connected to a memory socket on a server.

### Claim 5 (depends on 1)

The system of claim 1 wherein each offload processor modules is physically connected to a dual in line memory module (DIMM) socket on a server.

### Claim 6 (depends on 1)

The system of claim 1 wherein multiple offload processor modules are connected to multiple memory sockets on at least one of the servers.

### Claim 7 (depends on 1)

The system of claim 1 wherein the offload processors are configured to direct network packets to one or more of the offload processors based on availability of the offload processors.

### Claim 8 (depends on 1)

The system of claim 1 wherein the offload processor modules are connected to a memory bus on each of the servers, and are further configured to receive network packets from the server through a memory bus or from the IO port on the offload processing module.

### Claim 9

A rack server system for a map/reduce data processing, comprising:
a plurality of servers arranged in a rack,
a plurality of offload processor modules supported on at least two of the servers, each offload processor module having an input-output (IO) port and multiple offload processors, a first offload processor module configured to execute map steps of the map/reduce data processing, and being connected directly to a second offload processor through their respective IO ports to define a midplane switch, and
a top of rack (TOR) unit connected to each of the servers that does not transfer map/reduce data, wherein
a second offload processor module is configured to execute reduce steps of the map/reduce data processing on data provided from the first offload processor module.

### Claim 10 (depends on 9)

The system of claim 9 wherein each offload processor module is connected to a memory bus.

### Claim 11 (depends on 9)

The system of claim 9 wherein each offload processor module is connected to a memory bus on a server.

### Claim 12 (depends on 9)

The system of claim 9 wherein each offload processor module is physically connected to a memory socket on a server.

### Claim 13 (depends on 9)

The system of claim 9 wherein each offload processor module is physically connected to a dual in line memory module (DIMM) socket on a server.

### Claim 14 (depends on 9)

The system of claim 9 wherein multiple offload processor modules are connected to multiple memory sockets on at least one of the servers.

### Claim 15 (depends on 9)

The system of claim 9 wherein the first offload processor module is configured to generate virtual interrupts corresponding to the execution of the map steps.

### Claim 16 (depends on 9)

The system of claim 9 wherein the offload processors are configured to direct network packets to one or more of the offload processors based on availability of the offload processors.

### Claim 17 (depends on 9)

The system of claim 9 wherein the offload processor modules are connected to a memory bus on each of the servers, and are further configured to receive network packets from the server through a memory bus or from the IO port on the offload processing module.