# US 9,436,639 B1 · Full bandwidth packet handling with server systems including offload processors

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- Number: US 9,436,639 B1
- Document ID: US9436639B1
- Status: Granted
- Kind: B1
- Application number: 13/931,907
- Filed: 2013-06-29
- Granted: 2016-09-06
- Earliest claimed: 2013-01-17
- Assignees: Xockets, Inc.
- Applicants: Xockets, Inc.
- Inventors: Parin Bhadrik Dalal; Stephen Paul Belair
- Web page: https://patentgrep.com/patent/US9436639B1

## CPC

- G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/461: {Saving or restoring of program or task context}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 12/0815: Cache consistency protocols
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/285: {Halt processor DMA (G06F13/30 takes precedence)}
- G06F 13/362: with centralised access control
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4068: {Electrical coupling}
- G06F 15/161: {Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning (casings, cabinets, racks or drawers for data centers H05K5/00)}
- G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)}
- H04L 47/193: at the transport layer, e.g. TCP related
- H04L 47/2441: relying on flow classification, e.g. using integrated services [IntServ]
- H04L 47/56: implementing delay-aware scheduling
- H04L 47/624: {Altering the ordering of packets in an individual queue}
- H04L 47/6295: using multiple queues, one for each individual QoS, connection, flow or priority
- H04L 49/90: Buffering arrangements
- H04L 61/103: across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
- H04L 61/2592: using tunnelling or encapsulation
- H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46)
- H04L 67/1097: for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
- G06F 2212/1024: Latency reduction
- H04L 49/40: Constructional details, e.g. power supply, mechanical construction or backplane
- H04L 2101/686: using dual-stack hosts, e.g. in Internet protocol version 4 [IPv4]/Internet protocol version 6 [IPv6] networks
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A distributed system server system for a packet processing without top of rack (TOR) units is disclosed. The system can include a plurality of servers, each having at least one host processor, and a plurality of offload processor modules, each offload processor module having an input-output (IO) port and multiple offload processors, wherein a first offload processor module is connected directly to a second offload processor module through respective IO ports, the first and second offload processors configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without TOR units for an inter-server connection.

## Claims

### Claim 1

A distributed system server system for a packet processing without top of rack (TOR) units, comprising:
a plurality of servers, each server having
at least one host processor, and
a plurality of offload processor modules, each offload processor module being connected to memory bus on the server and having an input-output (IO) port and multiple offload processors, each offload processor module also configured to receive network packets from one of the servers through a memory bus and the IO port on the offload processing module; and
a memory controller configured to send network packet data directly to at least one offload processor module via the memory bus to which the offload processor module is attached; wherein
a first of the offload processor modules is connected directly to a second of the offload processor modules through the IO ports of the first and second processor modules, the first and second offload processor modules configured to provide bidirectional network packet flow between at least the first and second offload processor modules and at least one host processor without use of a TOR unit for an inter-server connection.

### Claim 2 (depends on 1)

The system of claim 1 wherein each offload processor module is physically connected to a memory socket on a server.

### Claim 3 (depends on 1)

The system of claim 1 wherein each offload processor module is physically connected to a dual in line memory module (DIMM) socket on a server.

### Claim 4 (depends on 1)

The system of claim 1 wherein multiple offload processor modules are connected to multiple memory sockets on at least one of the servers.

### Claim 5 (depends on 1)

The system of claim 1 wherein at least one offload processor module is configured as a midplane switch to forward network packets to one or more of the multiple offload processor modules.

### Claim 6 (depends on 1)

The system of claim 1 wherein the offload processors are configured to direct network packets to one or more of the offload processors based on availability of the offload processors.

### Claim 7 (depends on 1)

The system of claim 1, wherein each offload processor module further comprises a scheduler configured to determine a routing of network packets through respective IO ports of the offload processor modules based on availability of offload processors.