# US 9,436,632 B2 · Accessing data stored in a command/address register device

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- Number: US 9,436,632 B2
- Document ID: US9436632B2
- Status: Granted
- Kind: B2
- Application number: 14/560,976
- Filed: 2014-12-04
- Published: 2015-03-26
- Granted: 2016-09-06
- Earliest claimed: 2014-12-04
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Kuljit S. Bains; Klaus J. Ruff; George Vergis; Suneeta Sah
- Web page: https://patentgrep.com/patent/US9436632B2

## CPC

- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0787: {Storage of error reports, e.g. persistent data storage, storage using memory protection}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/1612: {where the redundant component is persistent storage}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 2029/0411: {Online error correction}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

## Claims

### Claim 1

An apparatus comprising:
a dynamic random access memory (DRAM) comprising at least one page having at least one multipurpose register (MPR) and comprising:
a first interface that, when operatively coupled to an address bus, is to receive a control word (CW) and provide the CW to a particular MPR and
a second interface communicatively coupled to the at least one page having at least one MPR, wherein:
the at least one page having at least one MPR to be written-to using the first interface during a coupling of the first interface to the address bus and to be read-from using the second interface during a coupling of the second interface to a data bus.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the CW comprises a 4-bit CW or an 8-bit CW.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the particular MPR comprises an MPR number zero (MPR0) of page 0 and the CW is associated with a command CMD4.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the CW is associated with a read operation,
the read operation is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the CW is associated with a read operation with auto-increment of an address field,
the read operation with auto-increment of an address field is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising:
an address bus communicatively coupled to the first interface;
a register communicatively coupled to the address bus; and
a memory controller communicatively coupled to the register, the memory controller to:
provide the CW to the register,
select a page and MPR within the selected page to receive the CW, and
provide one or more commands to cause writing of the CW to the selected page and MPR.

### Claim 7 (depends on 6)

The apparatus of claim 6, further comprising:
a data bus communicatively coupled to the second interface and
a processor communicatively coupled to the data bus, wherein:
the data bus interface is to provide content from an MPR to the processor via the data bus.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the register is to perform parity checking.

### Claim 9

A computer-implemented method comprising:
receiving, at a multipurpose register (MPR), a control word (CW) from an address bus interface, wherein the MPR is associated with a dynamic random access memory (DRAM) and wherein the CW is received during a coupling of the address bus interface with an address bus, and
transmitting content from the MPR using a data bus interface during a coupling of the data bus interface with a data bus.

### Claim 10 (depends on 9)

The method of claim 9, wherein the CW comprises a 4-bit CW or an 8-bit CW.

### Claim 11 (depends on 9)

The method of claim 9, wherein the MPR comprises an MPR number zero (MPR0) of a page 0 and the CW is associated with a command CMD4.

### Claim 12 (depends on 9)

The method of claim 9, wherein:
the CW is associated with a read operation,
the read operation is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 13 (depends on 9)

The method of claim 9, wherein:
the CW is associated with a read operation with auto-increment of an address field,
the read operation with auto-increment of an address field is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 14

An apparatus to write a control word (CW), the apparatus comprising:
a register;
a memory controller to provide a command, the command to cause the register to write a CW to at least one multipurpose register (MPR) associated with a dynamic random access memory (DRAM); and
an address bus interface communicatively coupled to the register, the address bus interface to provide the CW for transfer to an MPR associated with the command.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the command comprises a command CMD4 to send a CW to MPR0 of page 0 and the MPR0 of page 0 is to receive the CW from an address bus.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein:
the CW is associated with a read operation,
the read operation is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 17 (depends on 14)

The apparatus of claim 14, wherein:
the CW is associated with a read operation with auto-increment of an address field,
the read operation with auto-increment of an address field is associated with an 8-bit value having positions [7:0] and having at least an MPR bit 1 in position 6 and an MPR bit 0 in position 5, and
a combination of MPR bit 1 and bit 0 to select a particular MPR number.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein the memory controller comprises any or a combination of: software executed by one or more processors, hardware, or firmware.

### Claim 19 (depends on 14)

The apparatus of claim 14, further comprising:
a memory device comprising the DRAM, the DRAM comprising at least one page having at least one MPR;
an address bus communicatively coupled to the address bus interface and to the memory device;
a data bus communicatively coupled to the at least one MPR; and
a processor communicatively coupled to the data bus, wherein the MPR is to provide content to the processor via the data bus.

### Claim 20 (depends on 19)

The apparatus of claim 19, further comprising:
a physical layer logic;
a radio communicatively coupled to the physical layer logic;
at least one antenna communicatively coupled to the radio; and
a display communicatively coupled to the processor.