# US 9,436,631 B2 · Chip including memory element storing higher level memory data on a page by page basis

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- Number: US 9,436,631 B2
- Document ID: US9436631B2
- Status: Granted
- Kind: B2
- Application number: 14/231,358
- Filed: 2014-03-31
- Published: 2014-10-02
- Granted: 2016-09-06
- Earliest claimed: 2001-03-05
- Assignees: Pact Xpp Technologies AG
- Applicants: Pact Xpp Technologies AG
- Inventors: Martin Vorbach
- Web page: https://patentgrep.com/patent/US9436631B2

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/36: for access to common bus or bus system
- G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer.

## Claims

### Claim 1

A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:
a plurality of bus segments for each processor of the multiprocessor system comprising a plurality of flexible data channels to each processor of the multiprocessor system according to algorithms to be executed, wherein a plurality of algorithms may executed in parallel;
wherein a communication between a sender and a receiver is established in accordance with a data transfer for an executed algorithm; and
at least one identifier is transmitted with the data for at least one of: identifying a source of the data transfer; and selecting a target of the data transfer.

### Claim 2 (depends on 1)

The bus system of claim 1, wherein at least one of the parts of the multiprocessor system is a cache memory.

### Claim 3 (depends on 2)

The bus system of claim 2, wherein the cache memory comprises a plurality of cache cores.

### Claim 4 (depends on 3)

The bus system of claim 3, wherein the cache cores are connected to the bus system such that for the data transfer one of the cache cores is selected according to an address transferred via the bus system;
wherein at least some of the plurality of cache cores are combined to form a large cache.

### Claim 5 (depends on 1)

The bus system of claim 1 further comprising:
at least one buffer storing address data for performing a second data transfer if the data transfer fails.

### Claim 6 (depends on 5)

The bus system of claim 5, wherein the buffer has a read pointer and a write pointer.

### Claim 7 (depends on 6)

The bus system of claim 6, wherein if the data transfer fails, the read pointer is reset to the starting point of the data transfer and the second data transfer is performed.

### Claim 8 (depends on 1)

The bus system of claim 1, wherein one identifier is transmitted for identifying the source of the data transfer.

### Claim 9 (depends on 1)

The bus system of claim 1, wherein one identifier is transmitted for selecting the target of the data transfer.

### Claim 10 (depends on 1)

The bus system of claim 1, wherein at least two identifiers are transmitted for (a) identifying the source of the data transfer; and (b) selecting the target of the data transfer.

### Claim 11 (depends on 1)

The bus system of claim 1, wherein the bus system connects a plurality of parts of the multiprocessor system with at least one peripheral.

### Claim 12 (depends on 1)

The bus system of claim 1, wherein the bus system connects at least one part of the multiprocessor system with at least one memory.

### Claim 13 (depends on 1)

The bus system of claim 1, wherein the bus system connects at least two processors.

### Claim 14

A bus system for transferring data between parts of a multiprocessor system, the bus system comprising:
a plurality of bus segments for each processor of the multiprocessor system comprising a plurality of flexible data channels to each processor of the multiprocessor system;
wherein a communication between a sender and a receiver is established in accordance with a data transfer; and
at least one identifier is transmitted with the data for at least one of: identifying a source of the data transfer; and selecting a target of the data transfer.