# US 9,436,630 B2 · Using dual phys to support multiple PCIe link widths > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,630 B2 - Document ID: US9436630B2 - Status: Granted - Kind: B2 - Application number: 14/026,062 - Filed: 2013-09-13 - Published: 2014-12-11 - Granted: 2016-09-06 - Earliest claimed: 2013-06-11 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Farooq Yousuf - Web page: https://patentgrep.com/patent/US9436630B2 ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/1678: {using bus width} - G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)} - G06F 13/1694: {Configuration of memory controller to different memory types} - G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a host interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices. ## Claims ### Claim 1 A storage device, comprising: a plurality of non-volatile solid state memory devices; a set of Peripheral Component Interconnect Express (PCIe) connectors configured to receive memory access commands from a host system; and a controller configured to receive and process memory access commands for accessing the plurality of non-volatile solid state memory devices, the controller comprising a host interface, the host interface comprising: a plurality of physical interfaces (PHYs), each PHY configured to communicate with a subset of PCIe connectors from the set of PCIe connectors, wherein at least one of the plurality of PHYs comprises a dual PCIe PHY, thereby enabling the host interface to be used with multiple PCIe topologies; and one or more PCIe cores configured to process signals passing through the plurality of PHYs. ### Claim 2 (depends on 1) The storage device of claim 1, wherein each PHY comprises a clock multiplier unit configured to multiply a frequency of a clock signal received at the host interface while maintaining synchronicity with a provider system of the clock signal. ### Claim 3 (depends on 2) The storage device of claim 2, wherein the host interface further comprises a synchronizer configured to synchronize a clock signal of each PHY. ### Claim 4 (depends on 3) The storage device of claim 3, wherein the synchronizer is configured to synchronize the clock signal of each PHY by: selecting a PHY from the plurality of PHYs; synchronizing the clock signal of each PHY based at least partially on the clock multiplier unit of the selected PHY; and deactivating the clock multiplier unit of each remaining PHY from the plurality of PHYs. ### Claim 5 (depends on 1) The storage device of claim 1, wherein the host interface further comprises a set of selectors, each selector associated with a corresponding PHY from the plurality of PHYs. ### Claim 6 (depends on 5) The storage device of claim 5, wherein at least one selector from the set of selectors is configured to select a PCIe core from the one or more PCIe cores to receive a data/command signal from the corresponding PHY based at least partially on a selector signal provided to the selector. ### Claim 7 (depends on 6) The storage device of claim 6, wherein the host interface further comprises a host processor, the host processor configured to provide the selector signal to the selector. ### Claim 8 (depends on 5) The storage device of claim 5, wherein at least one selector from the set of selectors is associated with one PCIe core from the one or more PCIe cores, the at least one selector configured to maintain a degree of latency for a signal path associated with the at least one selector. ### Claim 9 (depends on 5) The storage device of claim 5, wherein the host interface further comprises a latency unit associated with a first PHY from the plurality of PHYs, the latency unit configured to maintain a first signal latency between the first PHY and a first corresponding PCIe core from the one or more PCIe cores that matches a second signal latency, the second signal latency associated with a signal latency between a second PHY from the plurality of PHYs and a second corresponding PCIe core from the one or more PCIe cores. ### Claim 10 (depends on 1) The storage device of claim 1, wherein the set of PCIe connectors comprise a set of differential input/output connectors. ### Claim 11 (depends on 1) The storage device of claim 1, wherein each PCIe core from the one or more PCIe cores is associated with a separate root complex of a host system. ### Claim 12 (depends on 1) The storage device of claim 1, wherein the controller is a solid state driver controller. ### Claim 13 (depends on 1) The storage device of claim 1, wherein at least one PHY is not a dual PCIe PHY. ### Claim 14 (depends on 1) The storage device of claim 1, wherein the controller further comprises a memory controller configured to communicate with the host interface and the plurality of non-volatile solid state memory devices. ### Claim 15 A controller for a Peripheral Component Interconnect Express (PCIe) card, the controller comprising: a plurality of physical interfaces (PHYs), each PHY configured to communicate with a subset of PCIe connectors from a set of PCIe connectors, wherein at least one PHY supports a different number of PCIe connectors than at least one other PHY, thereby enabling the controller to be used with multiple PCIe card topologies; and one or more PCIe cores configured to communicate with the plurality of PHYs. ### Claim 16 (depends on 15) The controller of claim 15, wherein each PHY comprises a clock multiplier unit configured to modify a clock signal received at the controller while maintaining synchronicity with a provider system of the clock signal. ### Claim 17 (depends on 16) The controller of claim 16, further comprising a synchronizer configured to synchronize a clock signal of each PHY. ### Claim 18 (depends on 17) The controller of claim 17, wherein the synchronizer is configured to synchronize the clock signal of each PHY by: selecting a PHY from the plurality of PHYs; synchronizing the clock signal of each PHY using the clock multiplier unit of the selected PHY; and deactivating the clock multiplier unit of each remaining PHY from the plurality of PHYs. ### Claim 19 (depends on 15) The controller of claim 15, further comprising a set of selectors, each selector associated with a corresponding PHY from the plurality of PHYs. ### Claim 20 (depends on 19) The controller of claim 19, wherein at least one selector from the set of selectors is configured to select a PCIe core from the one or more PCIe cores to receive a data/command signal from the corresponding PHY based at least partially on a selector signal provided to the selector. ### Claim 21 (depends on 19) The controller of claim 19, wherein at least one selector from the set of selectors modifies a signal latency of a signal communicated between a PHY from the plurality of PHYs and a corresponding PCIe core from the one or more PCIe cores without enabling the selection of an alternative PCIe core from the one or more PCIe cores. ### Claim 22 A controller comprising: a plurality of physical interfaces (PHYs), each PHY configured to communicate with a subset of serial interface connectors from a set of serial interface connectors, wherein at least one PHY supports a different number of serial interface connectors than at least one other PHY; and one or more processing cores configured to communicate with the plurality of PHYs. ### Claim 23 (depends on 22) The controller of claim 22, wherein each PHY comprises a clock multiplier unit configured to modify a clock signal received at the controller while maintaining synchronicity with a provider system of the clock signal. ### Claim 24 (depends on 23) The controller of claim 23, further comprising a synchronizer configured to synchronize a clock signal of each PHY. ### Claim 25 (depends on 24) The controller of claim 24, wherein the synchronizer is configured to synchronize the clock signal of each PHY by: selecting a PHY from the plurality of PHYs; synchronizing the clock signal of each PHY using the clock multiplier unit of the selected PHY; and deactivating the clock multiplier unit of each remaining PHY from the plurality of PHYs. ### Claim 26 (depends on 22) The controller of claim 22, further comprising a set of selectors, each selector associated with a corresponding PHY from the plurality of PHYs. ### Claim 27 (depends on 26) The controller of claim 26, wherein at least one selector from the set of selectors is configured to select a processing core from the one or more processing cores to receive a data/command signal from the corresponding PHY based at least partially on a selector signal provided to the selector. ### Claim 28 (depends on 26) The controller of claim 26, wherein at least one selector from the set of selectors modifies a signal latency of a signal communicated between a PHY from the plurality of PHYs and a corresponding processing core from the one or more processing cores without enabling the selection of an alternative processing core from the one or more processing cores.