# US 9,436,624 B2 · Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system

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- Number: US 9,436,624 B2
- Document ID: US9436624B2
- Status: Granted
- Kind: B2
- Application number: 13/952,092
- Filed: 2013-07-26
- Published: 2015-01-29
- Granted: 2016-09-06
- Earliest claimed: 2013-07-26
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Ziv Zamsky; Moshe Anschel; Itay Keidar; Itay S. Peled; Doron Schupper; Yakov Tokar
- Inventors: Ziv Zamsky; Moshe Anschel; Itay Keidar; Itay S. Peled; Doron Schupper; Yakov Tokar
- Web page: https://patentgrep.com/patent/US9436624B2

## CPC

- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.

## Claims

### Claim 1

A circuitry for a computing system, comprising:
a first load store unit (LSU);
a second LSU;
a memory arrangement;
the first LSU being connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus, the first bus arrangement further comprising a first address bus connecting the first LSU and the memory arrangement;
the second LSU being connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus;
wherein the circuitry is arranged to carry out a multiple load instruction to cause the first LSU to simultaneously read data from the memory arrangement via the first read bus and the second read bus; and
wherein the multiple load instruction causes the first LSU to read data from a first address of the memory arrangement propagated over the first address bus and to read data from a second address of the memory arrangement, the second address consecutive to the first address in the memory arrangement.

### Claim 2 (depends on 1)

The circuitry according to claim 1, wherein the first write bus and the second write bus are unidirectional buses arranged to write data to the memory arrangement and the first read bus and the second read bus are unidirectional buses arranged to read data from the memory arrangement.

### Claim 3 (depends on 1)

The circuitry according to claim 1, the memory arrangement comprising at least one of a cache, a RAM or an external memory.

### Claim 4 (depends on 1)

The circuitry according to claim 1, the circuitry comprising one or more additional LSUs.

### Claim 5 (depends on 4)

The circuitry according to claim 4, each of the one or more additional LSUs being connected to the memory arrangement via a bus arrangement comprising a write bus and a read bus, wherein the circuitry is arranged to carry out one or more multiple load instructions to read data via two or more of the read buses.

### Claim 6 (depends on 1)

The circuitry according to claim 1, further being arranged to carry out a multiple store instruction in parallel to the multiple load instruction.

### Claim 7

A load store unit (LSU) arrangement for a computing system, comprising:
a first LSU;
a second LSU;
the first LSU being connected to a memory arrangement via a first read bus, the first bus arrangement further comprising a first address bus connecting the first LSU and the memory arrangement; arrangement comprising a first write bus and a first read bus;
the second LSU being connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus;
wherein the LSU arrangement is arranged to carry out a multiple store instruction to cause the first LSU to simultaneously write data to the memory arrangement via the first write bus and the second write bus; and
wherein the multiple store instruction causes the first LSU to write data to a first address of the memory arrangement propagated over the first address bus and to write data to a second address of the memory arrangement, the second address consecutive to the first address in the memory arrangement.

### Claim 8 (depends on 7)

The LSU arrangement of claim 7, wherein the LSU arrangement is arranged to carry out a multiple load instruction to cause the second LSU to simultaneously read data from the memory arrangement via the first read bus and the second read bus.

### Claim 9 (depends on 8)

The LSU arrangement of claim 8, wherein the multiple load instruction and the multiple store instruction are carried out in parallel and data is transferred over the first write bus, the first read bus, the second write bus, and the second read bus simultaneously.

### Claim 10 (depends on 7)

The LSU arrangement of claim 7, wherein the first write bus and the second write bus are unidirectional buses arranged to write data to the memory arrangement and the first read bus and the second read bus are unidirectional buses arranged to read data from the memory arrangement.

### Claim 11

A circuitry for a computing system, comprising:
a first load store unit (LSU);
a second LSU;
a memory arrangement;
the first LSU being connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus, the first bus arrangement further comprising a first address bus connecting the first LSU and the memory arrangement;
the second LSU being connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus;
wherein the circuitry is arranged to carry out a multiple store instruction to cause the first LSU to simultaneously write data to the memory arrangement via the first write bus and the second write bus; and
wherein the multiple store instruction causes the first LSU to write data to a first address of the memory arrangement propagated over the first address bus and to write data to a second address of the memory arrangement, the second address consecutive to the first address in the memory arrangement.

### Claim 12 (depends on 11)

The circuitry of claim 11, wherein the circuitry is configured to carry out a multiple load instruction to cause the second LSU to simultaneously read data from the memory arrangement via the first read bus and the second read bus.

### Claim 13 (depends on 12)

The circuitry of claim 12, wherein the multiple load instruction and the multiple store instruction are carried out in parallel and data is transferred over the first write bus, the first read bus, the second write bus, and the second read bus simultaneously.

### Claim 14 (depends on 12)

The circuitry of claim 12, the second bus arrangement further comprising a second address bus connecting the second LSU and the memory arrangement, wherein the multiple load instruction causes the second LSU to read data from a first address of the memory arrangement propagated over the second address bus and to read data from a second address of the memory arrangement, the second address consecutive to the first address in the memory arrangement.

### Claim 15 (depends on 11)

The circuitry of claim 11, wherein the first write bus and the second write bus are unidirectional buses arranged to write data to the memory arrangement and the first read bus and the second read bus are unidirectional buses arranged to read data from the memory arrangement.