# US 9,436,615 B2 · Optimistic data read > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,615 B2 - Document ID: US9436615B2 - Status: Granted - Kind: B2 - Application number: 14/506,124 - Filed: 2014-10-03 - Published: 2016-04-07 - Granted: 2016-09-06 - Earliest claimed: 2014-10-03 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies Inc. - Inventors: Sergey Anatolievich Gorobets - Web page: https://patentgrep.com/patent/US9436615B2 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 2212/1024: Latency reduction - G06F 2212/2022: Flash memory - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices - G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A storage module may include a controller that is configured to perform a read operation to read data stored in at least one memory, where the data is associated with logical address information. In order to perform the read operation, the controller may be configured to retrieve a preliminary physical address associated with the logical address information, and initiate a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information. ## Claims ### Claim 1 A storage system comprising: at least one memory; and control circuitry in communication with the at least one memory, wherein the control circuitry, in order to perform a read operation to read data stored in the at least one memory, is configured to: identify logical address information associated with the data; retrieve a first physical address associated with the logical address information from a first address data structure of a plurality of address data structures; initiate a data retrieval process of the read operation for a first version of the data stored at the first physical address; retrieve a second physical address associated with the logical address from a second data structure of the plurality of address data structure; when the second physical address matches the first physical address, complete the read operation using the first version of the data; and when the second physical address does not match the first physical address, terminate the initiated data retrieval process and initiate a subsequent data retrieval process for a second version of the data stored at the final physical address. ### Claim 2 (depends on 1) The storage system of claim 1, wherein the first address data structure comprises a primary address data structure. ### Claim 3 (depends on 1) The storage system of claim 1, wherein the plurality of address data structures comprises a primary address data structure and a plurality of secondary address data structures, wherein the first address data structure comprises the primary address data structure or a first secondary address data structure of the plurality secondary address data structure, and wherein the second address data structure a second secondary address data structure of the plurality of secondary address data structures. ### Claim 4 (depends on 1) The storage system of claim 1, wherein the first physical address comprises a first preliminary physical address, and wherein the control circuitry is further configured to: determine that the second physical address matches the first preliminary address when the query of the second address data structure returns either mapping information identifying that the second address data structure does not have a logical-physical address mapping associated with the logical address information or a second preliminary physical address that matches the first preliminary physical address; and determine that the second physical address does not match the first preliminary physical address when the query of the second address data structure returns the second preliminary physical address and the second preliminary physical address does not match the first preliminary physical address. ### Claim 5 (depends on 1) The storage system of claim 1, wherein the at least one memory comprises a first memory and a second memory, the first memory configured with a higher bit-per-cell storage density than the second memory, wherein the first address data structure provides logical-physical address mapping for the first memory, and wherein the second address data structure provides logical-physical address mapping for the second memory. ### Claim 6 (depends on 1) The storage system of claim 1, wherein the second address data structure tracks changes to entries in the first address data structure. ### Claim 7 (depends on 1) The storage system of claim 1, wherein the at least one memory comprises a local memory that is internal to the controller, and wherein the second address data structure identifies whether a most recent version of the data is stored in the local memory. ### Claim 8 (depends on 1) The storage system of claim 1, wherein the control circuitry is further configured to: communicate with the at least one memory using a plurality of different channels; retrieve the second address data structure before initiating the data retrieval process when the control circuitry uses a same channel of the plurality of different channels to retrieve the second address data structure and initiate the data retrieval process. ### Claim 9 (depends on 1) The storage system of claim 1, wherein the control circuitry is further configured to: concurrently initiate the data retrieval process using a first channel and retrieve the second address data structure using a second channel. ### Claim 10 (depends on 1) The storage system of claim 1, wherein the control circuitry is further configured to receive, from a host system, a host read request identifying the logical address information, wherein when the second physical address matches the first physical address, the control circuitry is further configured to send the first version of the data to the host system to complete the read operation. ### Claim 11 (depends on 1) The storage system of claim 1, wherein the read operation comprises a background read operation, wherein the control circuitry is further configured to: identify the logical address information as part of the background read operation, and send the data to a new location in the at least one memory to complete the background read operation. ### Claim 12 (depends on 1) The storage system of claim 1, wherein one or more of the at least one memory comprises three-dimensional memory. ### Claim 13 (depends on 1) The storage system of claim 1, wherein the control circuitry is on the same substrate as memory elements of the at least one memory. ### Claim 14 (depends on 1) The storage system of claim 1, wherein the control circuitry is further configured to confirm a final physical address associates with the logical address information based on the retrieval of the second physical address from the second data structure. ### Claim 15 (depends on 14) The storage system of claim 14, wherein the control circuitry is further configured to send to the at least one memory one or more sense commands that instruct the at least one memory to sense the first version of the data stored at the first physical address before confirming the final physical address. ### Claim 16 (depends on 14) The storage system of claim 14, wherein the control circuitry is further configured to: confirm the final physical address prior to completion of the data retrieval process for the first version of the data at the first physical address. ### Claim 17 (depends on 14) The storage system of claim 14, wherein the control circuitry is further configured to: complete the data retrieval process for the first version of the data at the first physical address prior to confirmation of the final physical address. ### Claim 18 A method of accelerating a logical-to-physical address translation, the method comprising: performing in a storage system having at least one memory: receiving, from a host system, a host request identifying logical address information for data stored in the at least one memory; reading a preliminary physical address associated with the logical address information from a first data structure of a plurality of address data structures; initiating a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information; while continuing with the data retrieval process, querying a second address data structure of the plurality of address data structures to confirm the final physical address, the second address data structure different from the first address data structure; and when the final physical address does not match the preliminary physical address, terminating the initiated data retrieval process and initiating a subsequent data retrieval process for a second version of the data stored at the final physical address. ### Claim 19 (depends on 18) The method of claim 18, wherein the first address data structure comprises a primary address data structure, and the second address data structure comprises a secondary address data structure. ### Claim 20 (depends on 18) The method of claim 18, wherein the preliminary physical address comprises a first preliminary physical address, and wherein the method further comprises: in the storage system: determining that the final physical address matches the first preliminary address when querying the second address data structure returns either mapping information identifying that the second address data structure does not have a logical-physical address mapping associated with the logical address information or a second preliminary physical address that matches the first preliminary physical address; and determining that the final physical address does not match the first preliminary physical address when the second address data structure returns the second preliminary physical address and the second preliminary physical address does not match the first preliminary physical address. ### Claim 21 (depends on 18) The method of claim 18, wherein the at least one memory comprises a first memory and a second memory, the first memory configured with a higher bit-per-cell storage density than the second memory, wherein the first address data structure provides logical-physical address mapping for the first memory; and wherein the second address data structure provides logical-physical address mapping for the second memory. ### Claim 22 (depends on 18) The method of claim 18, wherein the second address data structure tracks changes to entries in the first address data structure. ### Claim 23 (depends on 18) The method of claim 18, further comprising: retrieving, with the controller, the second address data structure using a channel before initiating the data retrieval process using the channel. ### Claim 24 (depends on 18) The method of claim 18, further comprising: concurrently initiating the data retrieval process using a first channel and retrieving the second address data structure using a second channel. ### Claim 25 (depends on 18) The method of claim 18, further comprising: in the storage system: confirming the final physical address prior to completing the data retrieval process for the first version of the data at the preliminary physical address. ### Claim 26 (depends on 18) The method of claim 18, further comprising: in the storage system: completing the data retrieval process for the first version of the data at the preliminary physical address prior to confirming the final physical address.