# US 9,436,610 B2 · Enhanced pre-fetch in a memory management system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,610 B2 - Document ID: US9436610B2 - Status: Granted - Kind: B2 - Application number: 14/464,750 - Filed: 2014-08-21 - Published: 2015-02-26 - Granted: 2016-09-06 - Earliest claimed: 2013-08-23 - Assignees: STMicroelectronics International N.V. - Applicants: STMicroelectronics International N.V. - Inventors: Gilles Ries; Ennio Salemi; Sana Ben Alaya - Web page: https://patentgrep.com/patent/US9436610B2 ## CPC - G06F 12/0862: with prefetch - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1063: {the data cache being concurrently virtually addressed} - G06F 2212/304: In main memory subsystem - G06F 2212/507: using speculative control - G06F 2212/602: Details relating to cache prefetching - G06F 2212/684: TLB miss handling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit. ## Claims ### Claim 1 An electronic device comprising: a memory management unit configured to receive data requests associated with virtual addresses from data request initiators and to translate the virtual addresses into physical addresses in a main memory system by: obtaining address translation information from an address translation look-aside buffer in the memory management unit, sending page table walk requests to a page table descriptor in the main memory system and receiving address translation information from the page table descriptor, the page table walk requests including information that specifies an amount of further address translation information, the further address translation information being associated with data requests that are subsequent to a current data request, and receiving the further address translation information from the page table descriptor and storing the further address translation information for use in connection with the data requests that are subsequent to the current data request; wherein the memory management system comprising a cache unit is configured to: intercept the page table walk requests, modify content of the intercepted page table walk requests such that the information that specifies the amount of further address translation information is extended from a first amount to a second amount, the second amount being greater than the first amount, store the second amount of further address translation information, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit. ### Claim 2 (depends on 1) The electronic device of claim 1, wherein the cache unit providing the address translation information based upon the intercepted page table walk request being associated with the address translation information already stored in the cache unit serves to avoid the sending of the page table walk request to the page table descriptor and to avoid the reception of the further address translation information from the page table descriptor. ### Claim 3 (depends on 1) The electronic device of claim 1, wherein the memory management unit comprises an address prediction module configured to: determine an identity of a data request initiator, calculate, based on the identity of the data request initiator, an address stride prediction value, and provide the address stride prediction value to the cache unit; and wherein the cache unit is further configured to: receive the address stride prediction value, and perform the extension of the information that specifies an amount of further address translation information based on the address stride prediction value. ### Claim 4 (depends on 3) The electronic device of claim 3, wherein the address prediction module comprises a register that is configured to contain the identity of at least one data request initiator and information associated therewith, the information associated with the identity of the at least one data request initiator for enabling and disabling the cache unit to operate based on the identity. ### Claim 5 (depends on 3) The electronic device of claim 3, wherein the address prediction module comprises a register that is configured to contain the identity of at least one data request initiator and information associated therewith, the information associated with the identity of the at least one data request initiator for calculating an address stride prediction value. ### Claim 6 (depends on 1) The electronic device of claim 1, wherein the electronic device comprises a system-on-a-chip. ### Claim 7 (depends on 1) The electronic device of claim 1, wherein the electronic device comprises a microchip. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein the electronic device comprises a mobile media device. ### Claim 9 An article comprising: a memory management unit configured to: send page table walk requests to a page table descriptor in a main memory system and receive address translation information from the page table descriptor, the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information from the page table descriptor; and a cache unit configured to: intercept the page table walk requests, modify content of the intercepted page table walk requests such that the information that specifies the amount of further address translation information is extended from a first amount to a second amount, the second amount being greater than the first amount, store the second amount of further address translation information for use in connection with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit from a data request that is prior to the current data request. ### Claim 10 (depends on 9) The article of claim 9, wherein providing the address translation information based upon the intercepted page table walk request being associated with the address translation information already stored in the cache unit serves to avoid the sending of the page table walk request to the page table descriptor and to avoid the reception of the further address translation information from the page table descriptor. ### Claim 11 (depends on 9) The article of claim 9, wherein the memory management unit comprises an address prediction module configured to: determine an identity of a data request initiator, calculate, based on the identity of the data request initiator, an address stride prediction value, and provide the address stride prediction value to the cache unit; and wherein the cache unit is further configured to: receive the address stride prediction value, and perform the extension of the information that specifies an amount of further address translation information based on the address stride prediction value. ### Claim 12 (depends on 11) The article of claim 11, wherein the address prediction module comprises a register that is configured to contain the identity of at least one data request initiator and information associated therewith, the information associated with the identity of the at least one data request initiator for enabling and disabling the cache unit to operate based on the identity. ### Claim 13 (depends on 11) The article of claim 11, wherein the address prediction module comprises a register that is configured to contain the identity of at least one data request initiator and information associated therewith, the information associated with the identity of the at least one data request initiator for calculating the address stride prediction value. ### Claim 14 A method of operating an electronic device comprising: configuring a memory management unit to receive data requests associated with virtual addresses from data request initiators and to translate the virtual addresses into physical addresses in a main memory system by: obtaining address translation information from an address translation look-aside buffer in the memory management unit, sending page table walk requests to a page table descriptor in the main memory system and receiving address translation information from the page table descriptor, with the page table requests including information that specifies an amount of further address translation information, and with the further address translation information being associated with data requests that are subsequent to a current data request, and receiving the further address translation information from the page table descriptor and storing the further address translation information for use in connection with data requests that are subsequent to a current data request; intercepting the page table walk requests, using a cache unit; modifying content of the intercepted PTW requests such that the information that specifies the amount of further address translation information is extended from a first amount to a second amount, the second amount being greater than the first amount, using the cache unit; storing the second amount of further address translation information in the cache unit; and providing the address translation information from the cache unit to the memory management unit based upon the intercepted page table walk request being associated with address translation information already stored in the cache unit. ### Claim 15 (depends on 14) The method of claim 14, wherein providing the address translation information from the cache unit to the memory management unit based upon the intercepted page table walk request being associated with the address translation information already stored in the cache unit avoids sending a page table walk request to the page table descriptor and avoids reception of further address translation information from the page table descriptor. ### Claim 16 (depends on 14) The method of claim 14, further comprising: determining an identity of a data request initiator; calculating an address stride prediction value based upon the identity of the data request initiator; providing the address stride prediction value from the address prediction module to the cache unit; receiving the address stride prediction value at the cache unit; and performing the extension of the information that specifies an amount of further address translation information in the cache unit, based upon the address stride prediction value. ### Claim 17 (depends on 14) The method of claim 14, further comprising enabling the cache unit to operate based on the identity of the data request initiator. ### Claim 18 A method comprising: sending page table walk requests to a page table descriptor in a main memory system and receive address translation information from the page table descriptor, the page table walk requests including information that specifies an amount of further address translation information, using a memory management unit; receiving the further address translation information from the page table descriptor, using the memory management unit; intercepting the page table walk requests, using a cache unit; modifying content of the intercepted page table walk requests such that the information that specifies the amount of further address translation information is extended from a first amount to a second amount, the second amount being greater than the first amount, using the cache unit; storing the second amount of further address translation information for use in connection with data requests that are subsequent to a current data request, using the cache unit; providing the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit from a data request that is prior to the current data request. ### Claim 19 (depends on 18) The method of claim 18, wherein providing the address translation information based upon the intercepted page table walk request being associated with the address translation information already stored in the cache unit serves to avoid the sending of the page table walk request to the page table descriptor and to avoid the reception of the further address translation information from the page table descriptor. ### Claim 20 (depends on 18) The method of claim 18, further comprising: determining an identity of a data request initiator, using an address prediction module of the memory management unit; calculating, based on the identity of the data request initiator, an address stride prediction value, using the address prediction module; providing the address stride prediction value to the cache unit, using the address prediction module; receiving the address stride prediction value, using the cache unit; and performing the extension of the information that specifies an amount of further address translation information based on the address stride prediction value, using the cache unit.