# US 9,436,608 B1 · Memory nest efficiency with cache demand generation

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,436,608 B1
- Document ID: US9436608B1
- Status: Granted
- Kind: B1
- Application number: 14/620,240
- Filed: 2015-02-12
- Published: 2016-08-18
- Granted: 2016-09-06
- Earliest claimed: 2015-02-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Ansu A. Abraham; Daniel V. Rosa; Donald W. Schmidt
- Web page: https://patentgrep.com/patent/US9436608B1

## CPC

- G06F 12/0842: for multiprocessing or multitasking
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 2209/485: Resource constraint
- G06F 2212/1016: Performance improvement
- G06F 2212/313: In storage device
- G06F 2212/603: of operating mode, e.g. cache mode or local memory mode
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.

## Claims

### Claim 1

A computer program product for optimizing a memory nest for a workload by an operating system, the computer program product comprising:
a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining a cache/memory footprint of each work unit of the workload;
assigning a time slice to each work unit of the workload based on the cache/memory footprint of the work unit; and
executing the workload, on a processor, by providing each work unit access to the processor for the time slice assigned to the work unit.

### Claim 2 (depends on 1)

The computer program product of claim 1, wherein the time slice assigned to each work unit is greater than a minimum time slice and less than a maximum time slice.

### Claim 3 (depends on 2)

The computer program product of claim 2, wherein the time slice assigned to each work unit is inversely related to the cache/memory footprint of the work unit.

### Claim 4 (depends on 1)

The computer program product of claim 1, wherein the memory nest comprises a plurality of storage elements used to store data accessed by the processor during execution of each work unit and where each of the plurality of storage elements at a lower level in the memory nest uses a least recently used algorithm to determine what data to evict to another one of the plurality of storage elements at a higher level in the memory nest.

### Claim 5 (depends on 1)

The computer program product of claim 1, wherein the cache/memory footprint of each work unit is dynamically determined during or after execution of the work unit.

### Claim 6 (depends on 1)

The computer program product of claim 1, wherein the cache/memory footprint of each work unit is determined based on a number of cache misses and/or a memory nest level at which those misses were resolved.

### Claim 7

A computer system having a processor configured to execute a workload having one or more work units and a memory nest that includes a plurality of storage elements used to store data accessed by the processor during execution of the one or more work units; wherein the computer system is configured to perform a method comprising:
determining a cache/memory footprint of each work unit of the workload;
assigning a time slice to each work unit of the workload based on the cache/memory footprint of the work unit; and
executing the workload, on a processor, by providing each work unit access to the processor for the time slice assigned to the work unit.

### Claim 8 (depends on 7)

The computer system of claim 7, wherein the time slice assigned to each work unit is greater than a minimum time slice and less than a maximum time slice.

### Claim 9 (depends on 8)

The computer system of claim 8, wherein the time slice assigned to each work unit is inversely related to the cache/memory footprint of the work unit.

### Claim 10 (depends on 7)

The computer system of claim 7, wherein the cache/memory footprint of each work unit is determined during or after the execution of the work unit.

### Claim 11 (depends on 7)

The computer system of claim 7, wherein the cache/memory footprint of each work unit is determined based on a number of cache misses and/or a memory nest level at which those cache misses were resolved.