# US 9,436,607 B2 · Locking a cache line for write operations on a bus

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- Number: US 9,436,607 B2
- Document ID: US9436607B2
- Status: Granted
- Kind: B2
- Application number: 14/712,868
- Filed: 2015-05-14
- Published: 2015-09-03
- Granted: 2016-09-06
- Earliest claimed: 2010-10-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Stephen L. Blinick; Charles S. Cardinell; Roger G. Hathorn; Bernhard Laubli; Miguel A. Montoya; Timothy J. Van Patten
- Web page: https://patentgrep.com/patent/US9436607B2

## CPC

- G06F 12/0879: Burst mode
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/127: using additional replacement algorithms
- G06F 12/1475: {in a virtual system, e.g. with translation means}
- G06F 2212/1052: Security improvement
- G06F 2212/303: In peripheral interface, e.g. I/O adapter or channel
- G06F 2212/604: Details relating to cache allocation
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G06F 2212/657: Virtual address space management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

## Claims

### Claim 1

A computer program product for bursting writes in a cache, the computer program product comprising a non-transitory computer readable storage medium having computer readable program code embodied therein that executes to perform operations, the operations comprising:
allocating a cache line in cache for a target address;
setting a lock for the cache line;
writing data to the cache line while the lock for the cache line is set;
processing an interrupt while filling the cache line, wherein the lock prevents the data in the cache line from being cast out while the interrupt is being processed;
returning to the filling the cache line after completing the processing the interrupt; and
flushing all the data in the cache line to the target address over a bus in response to completing the writing to the cache line.

### Claim 2 (depends on 1)

The computer program product of claim 1, wherein the data in the cache line is flushed as part of a burst write to the target address.

### Claim 3 (depends on 1)

The computer program product of claim 1, wherein the operations further comprise:
removing the lock on the cache line in response to the flushing all the data in the cache line.

### Claim 4 (depends on 1)

The computer program product of claim 1, wherein the operations further comprise:
saving data in the cache line to a buffer before the writing to the cache line; and
copying the data from the buffer to the cache line after the flushing all the data in the cache line to the target address.

### Claim 5 (depends on 1)

The computer program product of claim 1, wherein the operations further comprise:
recording the target address;
performing error handling; and
executing a command to invalidate the data in the cache line allocated to the recorded target address in response to the performing error handling.

### Claim 6 (depends on 1)

The computer program product of claim 1, wherein the cache and the non-transitory computer readable storage medium are in an Input/Output (I/O) device wherein the I/O device connects on the bus to an external device, and wherein the data in the cache line is flushed in a burst write over the bus to the external device.

### Claim 7 (depends on 1)

The computer program product of claim 1, wherein the cache and the bus are in an Input/Output (I/O) device including a hardware component, and wherein the data in the cache line is flushed in a burst write to the hardware component in the I/O device.

### Claim 8

A method, comprising:
allocating a cache line in a cache for a target address;
setting a lock for the cache line;
writing data to the cache line while the lock for the cache line is set;
processing an interrupt while filling the cache line, wherein the lock prevents the data in the cache line from being cast out while the interrupt is being processed;
returning to the filling the cache line after completing the processing the interrupt; and
flushing all the data in the cache line to the target address over a bus in response to completing the writing to the cache line.

### Claim 9 (depends on 8)

The method of claim 8, wherein the data in the cache line is flushed as part of a burst write to the target address.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
removing the lock on the cache line in response to the flushing all the data in the cache line.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
saving data in the cache line to a buffer before the writing to the cache line; and
copying the data from the buffer to the cache line after the flushing all the data in the cache line to the target address.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
recording the target address;
performing error handling; and
executing a command to invalidate the data in the cache line allocated to the recorded target address in response to the performing error handling.

### Claim 13 (depends on 8)

The method of claim 8, wherein the cache is in an Input/Output (I/O) device wherein the I/O device connects on the bus to an external device, and wherein the data in the cache line is flushed in a burst write over the bus to the external device.

### Claim 14 (depends on 8)

The method of claim 8, wherein the cache and the bus are in an Input/Output (I/O) device including a hardware component in the I/O device, and wherein the data in the cache line is flushed in a burst write to the hardware component in the I/O device.

### Claim 15

A system in communication with an external device over a bus, comprising:
a processor;
a cache;
a computer readable storage medium having instructions executed by the processor to perform operations, the operations comprising:
allocating a cache line in the cache for a target address at the external device;
setting a lock for the cache line;
writing data to the cache line while the lock for the cache line is set;
processing an interrupt while filling the cache line, wherein the lock prevents the data in the cache line from being cast out while the interrupt is being processed;
returning to the filling the cache line after completing the processing the interrupt; and
flushing all the data in the cache line to the target address over the bus to the external device in response to completing the writing to the cache line.

### Claim 16 (depends on 15)

The system of claim 15, wherein the data in the cache line is flushed as part of a burst write to the target address.

### Claim 17 (depends on 15)

The system of claim 15, wherein the operations further comprise:
removing the lock on the cache line in response to the flushing all the data in the cache line.

### Claim 18 (depends on 15)

The system of claim 15, wherein the operations further comprise:
saving data in the cache line to a buffer before the writing to the cache line; and
copying the data from the buffer to the cache line after the flushing all the data in the cache line to the target address.

### Claim 19 (depends on 15)

The system of claim 15, wherein the operations further comprise:
recording the target address;
performing error handling; and
executing a command to invalidate the data in the cache line allocated to the recorded target address in response to the performing error handling.

### Claim 20 (depends on 15)

The system of claim 15, wherein the cache, the processor, and the computer readable storage medium are in an Input/Output (I/O) device wherein the I/O device connects on the bus to the external device, and wherein the data in the cache line is flushed in a burst write over the bus to the external device.

### Claim 21 (depends on 15)

The system of claim 15, wherein the cache, the processor, and the bus are in an Input/Output (I/O) device, wherein the external device comprises a hardware component in the I/O device, and wherein the data in the cache line is flushed in a burst write to the hardware component in the I/O device.