# US 9,436,605 B2 · Cache coherency apparatus and method minimizing memory writeback operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,605 B2 - Document ID: US9436605B2 - Status: Granted - Kind: B2 - Application number: 14/136,131 - Filed: 2013-12-20 - Published: 2015-06-25 - Granted: 2016-09-06 - Earliest claimed: 2013-12-20 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jeffrey D. Chamberlain; Vedaraman Geetha; Robert G. Blankenship; Yen-Cheng Liu; Adrian C. Moga; Herbert H. Hum; Sailesh Kottapalli - Web page: https://patentgrep.com/patent/US9436605B2 ## CPC - G06F 12/0817: using directory methods - G06F 12/0815: Cache consistency protocols - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for reducing or eliminating writeback operations. For example, one embodiment of a method comprises: detecting a first operation associated with a cache line at a first requestor cache; detecting that the cache line exists in a first cache in a modified (M) state; forwarding the cache line from the first cache to the first requestor cache and storing the cache line in the first requestor cache in a second modified (M′) state; detecting a second operation associated with the cache line at a second requestor; responsively forwarding the cache line from the first requestor cache to the second requestor cache and storing the cache line in the second requestor cache in an owned (O) state if the cache line has not been modified in the first requestor cache; and setting the cache line to a shared (S) state in the first requestor cache. ## Claims ### Claim 1 A method comprising: detecting a first operation associated with a cache line at a first requestor cache, the cache line being a block of date; detecting that a copy of the cache line exists in a first cache in a modified (M) state; forwarding the copy of the cache line from the first cache to the first requestor cache and storing the copy of the cache line in the first requestor cache in a second modified (M′) state; transitioning the copy of the cache line in the first cache to an invalid (I) state; detecting a second operation associated with the cache line at a second requestor cache; responsively forwarding the copy of the cache line from the first requestor cache to the second requestor cache and storing the copy of the cache line in the second requestor cache in an owned (O) state if the copy of the cache line has not been modified in the first requestor cache; and setting the copy of the cache line to a shared (S) state in the first requestor cache. ### Claim 2 (depends on 1) The method as in claim 1 wherein the M′ state indicates that a cache line has been modified in the first cache and read into the first requestor cache but has not yet been written back to memory. ### Claim 3 (depends on 1) The method as in claim 1 wherein the O state indicates that the second requestor cache has one of several valid copies of the cache line, but has the exclusive right to make changes to it. ### Claim 4 (depends on 3) The method as in claim 3 wherein the S state indicates that the first requestor cache has a shared copy of the cache line but do not currently have the right to make changes to it. ### Claim 5 (depends on 1) The method as in claim 1 wherein the first cache, the first requestor cache, and the second requestor cache are peer caches. ### Claim 6 (depends on 5) The method as in claim 5 wherein the first cache, the first requestor cache, and the second requestor cache are either all level 1 (L1) caches or all Level 2 (L2) caches. ### Claim 7 (depends on 1) The method as in claim 1 further comprising: storing and maintaining a directory cache to provide an indication as to whether the cache line is cached exclusively in a cache without requiring a read of directory bits from memory. ### Claim 8 (depends on 1) The method as in claim 1 wherein the first cache is located on a different processor from the first requestor cache, and/or the first requestor cache is located on a different processor from the second requestor cache, and/or the first cache is located on a different processor from the second requestor cache. ### Claim 9 (depends on 1) The method as in claim 1 wherein the first cache is located on a different core from the first requestor cache, and/or the first requestor cache is located on a different core from the second requestor cache, and/or the first cache is located on a different core from the second requestor cache. ### Claim 10 (depends on 1) The method as in claim 1 wherein each of the first cache, first requestor cache, and second requestor cache comprise caching agents communicating with a home agent. ### Claim 11 A processor comprising: a first caching agent to detect a first operation associated with a cache line at a first requestor cache, wherein the cache line being a block of data, and further detecting that a copy of the cache line exists in a first cache in a modified (M) state; a second caching agent to forward the copy of the cache line from the first cache to the first requestor cache, the first caching agent to store the copy of the cache line in the first requestor cache in a second modified (M′) state, and the second caching agent further to transition the copy of the cache line in the first cache to an invalid (I) state; a third caching agent to detect a second operation associated with the cache line at a second requestor cache; the first caching agent to responsively forward the copy of the cache line from the first requestor cache to the third caching agent, the third caching agent to store the copy of the cache line in the second requestor cache in an owned (O) state if the copy of the cache line has not been modified in the first requestor cache; and the first caching agent to transition the copy of the cache line to a shared (S) state in the first requestor cache. ### Claim 12 (depends on 11) The processor as in claim 11 wherein the M′ state indicates that a cache line has been modified in the first cache and read into the first requestor cache but has not yet been written back to memory. ### Claim 13 (depends on 11) The processor as in claim 11 wherein the O state indicates that the second requestor cache has one of several valid copies of the cache line, but has the exclusive right to make changes to it. ### Claim 14 (depends on 13) The processor as in claim 13 wherein the S state indicates that the first requestor cache has a shared copy of the cache line but do not currently have the right to make changes to it. ### Claim 15 (depends on 11) The processor as in claim 11 wherein the first cache, the first requestor cache, and the second requestor cache are peer caches. ### Claim 16 (depends on 15) The processor as in claim 15 wherein the first cache, the first requestor cache, and the second requestor cache are either all level 1 (L1) caches or all Level 2 (L2) caches. ### Claim 17 (depends on 11) The processor as in claim 11 further comprising: a directory cache to provide an indication as to whether the cache line is cached exclusively in a cache without requiring a read of directory bits from memory. ### Claim 18 (depends on 11) The processor as in claim 11 wherein the first cache is located on a different core from the first requestor cache, and/or the first requestor cache is located on a different core from the second requestor cache, and/or the first cache is located on a different core from the second requestor cache. ### Claim 19 A system comprising: a memory for storing instructions and data; a graphics processor for performing graphics operations in response to certain instructions; a network interface for receiving and transmitting data over a network; and a processor comprising: a first caching agent to detect a first operation associated with a cache line at a first requestor cache, wherein the cache line being a block of data, and further detecting that a copy of the cache line exists in a first cache in a modified (M) state; a second caching agent to forward the copy of the cache line from the first cache to the first requestor cache, the first caching agent to store the copy of the cache line in the first requestor cache in a second modified (M′) state, and the second caching agent further to transition the copy of the cache line in the first cache to an invalid (I) state; a third caching agent to detect a second operation associated with the cache line at a second requestor cache; the first caching agent to responsively forward the copy of the cache line from the first requestor cache to the third caching agent, the third caching agent to store the copy of the cache line in the second requestor cache in an owned (O) state if the copy of the cache line has not been modified in the first requestor cache; and the first caching agent to transition the copy of the cache line to a shared (S) state in the first requestor cache.